Abstract: A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.
Type:
Application
Filed:
August 10, 2001
Publication date:
February 28, 2002
Applicant:
Marathon Technologies Corporation, a Delaware corporation
Inventors:
Thomas D. Bissett, Paul A. Leveille, Erik Muench