Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
Type:
Grant
Filed:
May 15, 2022
Date of Patent:
February 13, 2024
Assignee:
Marlin Semiconductor Limited
Inventors:
Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
Type:
Application
Filed:
May 15, 2022
Publication date:
September 1, 2022
Applicant:
Marlin Semiconductor Limited
Inventors:
Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
Type:
Grant
Filed:
March 31, 2020
Date of Patent:
June 7, 2022
Assignee:
Marlin Semiconductor Limited
Inventors:
Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang