Abstract: In a two-dimensional magnetic recording (TDMR) system, a first finite impulse response (FIR) filter processes data read from a track of a magnetic medium by a first head using first filter tap values determined a priori independently of a second head. A second FIR filter processes data read from a track by the second head using second filter tap values determined a priori independently of the first head. An off-track detector detects whether one or more of the first and second heads is off of the tracks being read. A gain controller controls gains for the first and second FIR filters based on whether one or more of the first and second heads is off of the tracks being read.

Abstract: A server including data loading, data analysis, transformation and cleaning (TAC), and position estimation modules. The data loading module loads original position data (OPD) sets. OPD points of the OPD sets refer to positions of a wireless device in communication with a wireless station. The data loading module loads each OPD set based on an identifier of the wireless station in a corresponding one of the OPD sets. The data analysis module: determines an overall bounding area based on the OPD points; divides the overall bounding area into minimum bounding areas; and assigns the OPD points to the minimum bounding areas. The TAC module: transforms and cleans some of the OPD points to provide updated points, such that the updated points have a less number of points than the some of the OPD points. The position estimation module estimates a position of the wireless device based on the updated points.

Abstract: Aspects of the disclosure provide an apparatus having a processing circuit and a transceiver. The processing circuit is configured to generate a frame to have an extended subtype under a control type, configure a media access control (MAC) header of the frame to indicate an extended control frame format, and configure a field of the frame to be an extended subtype field according to the extended control frame format to carry an identification for the extended subtype. The extended subtype is defined in addition to a plurality of subtypes that are identifiable using a subtype field in the frame according to a control frame format. The transceiver is configured to transmit signals to carry the frame.

Abstract: System and methods are provided for performing image noise reduction. Color estimation of a pixel in an image is performed, wherein the image is stored in a data structure in a non-transitory computer-readable storage medium and the pixel has an initial pixel value. A pixel-block size is selected for pixel block similarity calculations based at least in part on the color estimation. One or more first pixel blocks associated with the pixel of the selected pixel-block size are determined. One or more first pixel block average values for the one or more first pixel blocks are calculated. A weighted average of the first pixel block average values is calculated. The data structure is updated by replacing the initial pixel value of the pixel with the weighted average of the first pixel black average values.

Abstract: Systems and techniques relating to repeated signal detection are described. A described technique includes receiving a signal including a first portion and a second portion, the first portion including a first received symbol and a second received symbol; detecting whether the first received symbol is repeated as the second received symbol using a maximum a posterior decision metric including a first component and a second component, the first component contributing to the decision metric in accordance with the first received symbol being repeated as the second received symbol, and the second component contributing to the decision metric in accordance with the first received symbol not being repeated as the second received symbol; determining a format based on whether or not the first received symbol was repeated; and processing the second portion of the signal in accordance with the format, as determined.

Abstract: A host assembly of a wireless device enters into a handshaking procedure with firmware of the wireless device to initiate entry into or exit from a host sleep mode. Before such entry or exit, the handshaking procedure may require the host assembly to send an initiation handshake signal to the firmware, and require the firmware to send a confirmation handshake signal back to the host assembly. Entry or exit may be delayed until after the confirmation signal is received. The confirmation signal may vary depending on the handshaking configuration and activation data, and the confirmation signal may vary depending on whether the wireless device is in a power save mode or not.

Abstract: An estimate of a multiple input, multiple output (MIMO) channel is computed, and an equalizer to be applied to signals received via the MIMO channel is computed. The equalizer is initialized based on the estimate of the MIMO channel. The equalizer is applied to a received signal, and the received signal is demodulated to generate a demodulated signal. The demodulated signal is decoded according to an error correction code to generate decoded data, and the decoded data is re-encoded according to the error correction code to generate re-encoded data. The re-encoded data is re-modulated to generate a re-modulated signal. The received signal is compared to the re-modulated signal, and the equalizer is updated based on the comparison. After updating the equalizer, the equalizer is applied to the received signal.

Abstract: An axial field motor and a method of assembling the motor are provided. The hard disk drive includes a spindle motor having a fluid dynamic bearing (FDB) motor hub, a hard disk drive housing and a base insert. The hard disk drive housing houses the spindle motor therewithin and has an upper housing and a base, the base including a first material. The base insert has ferromagnetic properties, includes a second material and has a flat circular bottom portion and an outer circumferential vertical portion. The flat circular bottom portion of the base insert is located between the FDB motor hub and the base to enhance yield strength therebetween and a bottom portion of the FDB motor hub is surrounded by the outer circumferential vertical portion of the base insert to generate preload for the FDB motor hub.

Abstract: Systems, methods, and apparatus are provided for improving the iterative decoding performance of a decoder, for example, as used in a wireless communications receiver or in a data retrieval unit. A decoding technique may receive and process a set of channel samples using an iterative decoder. If the iterative decoder output indicates a decoding failure, noise samples may be combined with the received channel samples to create biased channel samples. Noise samples may be generated using a pseudo-random noise generator and/or by using signals already present in the communications receiver or data retrieval unit. The biased channel samples may be provided to the iterative decoder and the iterative decoder may re-run using the biased channel samples.

Abstract: A wireless network device comprises a first wireless communication device that includes a first radio frequency (RF) transceiver that generates a synchronization pulse and that transmits and receives data according to a first period. A second wireless communication device receives a signal indicative of the synchronization pulse and includes a second RF transceiver that transmits and receives data according to a second period. The second period is not equal to the first period and the second wireless communication device adjusts the second period according to the first period and the synchronization pulse.

Abstract: A physical layer (PHY) device of a network device includes a signal generator module that generates a first test signal and that transmits the first test signal on a first conductor of a first pair of a cable at time T1, an analog-to-digital converter (ADC) module that has an input that communicates with a second conductor of the cable and an output that generates first S outputs at times (T1+(S*t)), where S is greater than 1, and t>0, and a control module that determines a distance from the PHY to one of an open-circuit and short-circuit of the first pair based on the first S outputs.

Abstract: An alarm monitor includes memory that stores an actuator schedule. An input circuit receives a sensor signal that indicates an alarm condition, the sensor signal originating from a sensor that is remote from the alarm monitor. A processor generates digital data based on the sensor signal and generates a first control signal to control an actuator based on the actuator schedule. An interface wirelessly transmits a report signal to a remote master unit based on the digital data and transmits the first control signal to the actuator.

Abstract: A system and method for determining the rotational speed of a motor, such as a three-phase disk drive motor, detects back electromotive force voltage generated during operation of the motor with an automatic pole calibration to minimize or eliminating variations in the wave of a freeze signal. A phase voltage at a winding is compared against a center tap (CT) voltage. Once the phase voltage falls to a specified voltage level, a detect signal is generated. A predetermined time after the detect signal is generated, a freeze signal is generated for freezing at least the circuit associated with the winding.

Abstract: A distortion correction circuit comprises memory that stores N samples of an input signal that occur at N different times, where N is an integer greater than two. A self-receiver samples an output signal that is generated by an RF power amplifier and that is based on said input signal. A synchronization unit selects one of said N samples by comparing said sampled output signal to said N samples. A predistortion unit generates a distortion correction function based on said selected one of said N samples and said output signal.

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.

Abstract: A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

Abstract: A servo channel digitally processes the data read from a magnetic media. The channel uses both edges of a system clock to detect peaks and generates position error systems by an area-based automatic gain control loop. By altering the sample delay, the channel digitally, up-samples at higher rates without requiring a higher system clock.