Abstract: Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data.

Abstract: Aspects of the disclosure provide a method for tuning delay. The method includes driving, during a calibration stage, at least one test signal from an integrated circuit onto a plurality of outside transmission lines that are coupled to the integrated circuit, measuring a timing of the at least one test signal transmitted and reflected over the plurality of outside transmission lines, and selectively delaying, using units disposed within the integrated circuit, signals subsequently transmitted over the plurality of outside transmission lines based on the timing of the at least one test signal, in order to align transmission times of the subsequently transmitted signals.

Abstract: The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage.