Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. Correction control circuitry is configured to control gain control circuitry based on the asymmetrical signal to adjust a gain of the amplifier to correct the asymmetric signal. A first adjustment of the gain control circuitry is performed during a first interval and a second adjustment of the gain control circuitry is performed during a second interval to correct the asymmetric signal.

Abstract: Power-saving and area-efficient BCH coding systems are provided that employ hybrid decoder architectures. The BCH decoder architectures comprise both special-purpose hardware and firmware, thereby taking advantage of both the speed of special-purpose hardware and the energy-efficiency of firmware. In particular, the error correction capabilities of the BCH decoders provided herein are split between a hardware component designed to correct a single error and a firmware component designed to correct the remaining errors. In this manner, firmware operation is bypassed in situations where only one error is present and the complexity of the necessary hardware is significantly reduced.

Abstract: Systems and techniques for digital processing of FM stereo signals are described. A carrier signal such as a 38 kHz carrier may be recovered and used to process a difference signal such as a left minus right signal. The left minus right signal and a left plus right signal may be used to generate separate left plus right signals.

Abstract: A high speed write driver for an inductive head of a magnetic storage medium is provided which contains a mechanism to reduce the inductive head current overshoot and therefore reduce jitter and, thus, increase the write cycle frequency. An input voltage control stage controls a voltage applied to the inductive head from the voltage source. A current supply to supplies current to the inductive head element, and a damping circuit in communication with the inductive head element. An overshoot suppressor circuit is provided such that the input voltage control tage is responsive to the overshoot suppressor circuit.