Abstract: A system comprising includes a clock generator module, an analog-to-digital converter (ADC), and a correction module. The clock generator module receives a system clock and generates a digital clock that is derived from the system clock, wherein the digital clock has an average frequency. The clock generator module generates a deviation indication that indicates a deviation of the digital clock from an ideal clock of the average frequency. The ADC receives an analog signal, receives the digital clock, and generates a first stream of values by sampling the analog signal at intervals based on the digital clock. The correction module receives the first stream of values and generates a second stream of values that are corrected based on the deviation indication.

Abstract: A digital interface system that includes a first circuit that transmits a set of voltage levels and a second circuit that receives the set of voltage levels and generates a set of voltage differential levels based on the set of voltage levels. The set of voltage differential levels corresponds to a first predetermined value. Each of the voltage levels is different from another of the voltage levels.

Abstract: An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m?2 and n?m. A clock driver is adapted to provide m domain clock signals and m switching units, each adapted to provide one of the m domain clock signals to the storage elements in a respective one of the m clock domains in response to a first state of a scan mode signal, and to provide a single scan clock signal to the n storage elements in the m clock domains in response to a second state of the scan mode signal. The n storage elements are adapted to interconnect in series in response to a scan shift signal and to serially shift bits through the scan chain in response to the scan clock signal when the scan to mode signal is in the second state.