Abstract: Aspects of the disclosure provide a network device that includes interface circuitry and packet processing circuitry. The interface circuitry is configured to receive incoming packets from a network and transmit outgoing packets to the network via interfaces. The packet processing circuitry is configured to detect a congestion associated with a packet that is sent from a source device to a destination device in the network and generate a notification packet that is destined to the source device. The notification packet is indicative of a packet flow that the packet belongs to and the presence of the congestion. The packet processing circuitry is configured to send the packet to the destination device via a first interface and send the notification packet to the source device via a second interface.

Abstract: Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.

Abstract: A plurality of packets that belong to a data flow are received and are distributed to two or more packet processing elements, wherein a packet is sent to a first packet processing element. A first instance of the packet is queued at a first packet processing element according to an order of the packet within the data flow. The first instance of the packet is caused to be transmitted when processing of the first instance is completed and the first instance of the packet is at a head of a queue at the first ordering unit. A second instance of the packet is queued at a second ordering unit. The second instance of the packet is caused to be transmitted when processing of the second instance is completed and the second instance of the packet is at a head of a queue at the second ordering unit.

Abstract: Aspects of the disclosure include an integrated circuit that includes a first circuit, a first performance detector, and a first regulator. The first circuit is configured to receive a first regulated voltage from a first voltage supply line disposed on the integrated circuit. The first performance detector includes a first speed monitor disposed adjacent to the first circuit, and the first performance detector is configured to generate a first control signal based on a first speed detection result from the first speed monitor. The first speed detection result corresponds to measuring an operational speed of the first circuit. The first regulator is configured to receive a global supply voltage from a power rail and output the first regulated voltage based on the global supply voltage and the first control signal.

Abstract: Aspects of the disclosure provide an integrated circuit and method for varying a frequency of a clock signal to accommodate critical paths in the integrated circuit. The integrated circuit can include a clock generator configured to generate a clock signal having a clock frequency that is variable, circuitry that includes a plurality of critical modules that can be selectively activated to operate under control of the clock signal, each critical module including one or more critical paths that a default clock frequency cannot accommodate, and a controller that causes the clock generator to vary the clock frequency of the clock signal based on propagation delays of those critical paths in activated critical modules.

Abstract: In a method for storing packets in a network device, a memory space spanning a plurality of external memory devices is partitioned into a plurality of multi-buffers. Each multi-buffer spans multiple memory devices in the plurality of external memory devices. Each multi-buffer is partitioned into a plurality of buffer chunks and the plurality of buffer chunks are distributed among the multiple memory devices Further, a packet is divided into one or more packet chunks including at least a first packet chunk. The one or more packet chunks are stored in one or more consecutive buffer chunks of at least a first multi-buffer of the plurality of multi-buffers.

Abstract: Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal. A voltage reference level shifter is configured to selectively level shift the voltage reference signal supplied to the amplifier based on a type of device with which the receiver is communicating. A data signal level shifter is configured to selectively level shift the data signal supplied to the amplifier based on the type of device with which the receiver is communicating.

Abstract: In a data transfer interface, at least one deserializer receives a serial data stream at a first clock speed and outputs a first parallel data stream at a second clock speed. The first parallel data stream includes data symbols representing data and alignment symbols for aligning the data symbols at a downstream location. A demultiplexer demultiplexes the first parallel data stream into a plurality of second parallel data streams based on the alignment symbols.