Abstract: An integrated circuit and a method for efficiently operating integrated circuit devices. The integrated circuit includes an input that is configured to receive a first current which is representative of a leakage current drawn by leakage in a portion of the integrated circuit. The integrated circuit includes a leakage calibrator that is configured to compare the first current to a current required to perform a switching operation and output a value indicative of the leakage.

Abstract: A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a scrambler configured to provide a driving address and associated data to an envelope based on a memory configuration for using a memory array. The driving address and the associated data are used to test the memory array according to a test pattern. The envelope is configured to translate the driving address into a corresponding physical address of the memory array based on the memory configuration.

Abstract: Embodiments of the present disclosure provide a method for tuning an analog equalizer and a digital equalizer associated with a communications channel. A plurality of signals is injected into a model of a communication channel, the model being configured to have an analog equalizer at a receiving end, tuning a setting of the analog equalizer to obtain a first ratio of a pulse peak to a rise time in a precursor portion of the injected plurality signals that are received from the channel, injecting another plurality of signals into the model of the communication channel, the model being reconfigured to have the tuned analog equalizer and a digital equalizer downstream of the tuned analog equalizer, and tuning a setting of the digital equalizer based on a post-cursor tail characteristic of the another plurality of signals. Other embodiments are also described and claimed.

Abstract: Systems and techniques for improved bus control, which may be particularly useful for double data rate (DDR) data transfer. A circuit may include a clock transmitter in communication with a clock bus, a clock receiver in communication with the clock bus, and a driver in communication with the clock bus. The driver may drive a voltage of the clock bus to a first voltage level when the clock transmitter is not transmitting a clock signal on the clock bus and the clock receiver is not receiving a clock signal on the clock bus.

Abstract: A method and a computer readable medium having executable instructions are provided. The method and instructions when executed generates a first look-up key from a group of look-up key units stored in a data storage, generation of the first look up key being completed prior to the completion of a key generation processing cycle. A next look-up key unit from the group of look-up key units stored in the data storage may be skipped over when the next look up key corresponds to a second look-up key that has a key length equal to or smaller than a predetermined key length. A third look-up key unit may be selected from the group of look-up key units, the third look-up key unit associated with a third look-up key having a key length greater than a second predetermined key length, the second predetermined key length being greater than the first predetermined key length. The first look-up key and a portion of the third look-up key sequentially may be output during the same output processing cycle.

Abstract: A data processing system includes a memory configured to store data in a plurality of addressable storage spaces thereof, wherein the memory includes a first data port and a second data port, a first functional block configured to access the memory via the first data port to perform a logic operation, and a second functional block configured to access the memory via the second data port to perform soft error scrubbing in the data stored in the memory.

Abstract: Systems and apparatus for managing buffers in a buffer memory are described. In at least one aspect, a system includes a buffer memory including a plurality of buffers; an allocation memory including a plurality of allocation data elements associated with the plurality of buffers; an allocation clear register coupled with the allocation memory; a reclaim memory including a plurality of reclaim data elements each associated with an allocation data element and corresponding buffer; a reclaim clear register coupled with the reclaim memory; an allocation register configured to receive one or more allocation data elements from the allocation memory; and a buffer manager.

Abstract: An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.

Abstract: Some of the embodiments of the present disclosure provide a command processing pipeline to be operatively coupled to a shared cache, the command processing pipeline comprising a command processing pipeline operatively coupled to the N-way cache and configured to process a sequence of cache commands, wherein a way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way. Other embodiments are also described and claimed.

Abstract: An integrated circuit and a method for efficiently operating integrated circuit devices. The integrated circuit includes an input that is configured to receive a first current which is representative of a leakage current drawn by leakage in a portion of the integrated circuit. The integrated circuit includes a leakage calibrator that is configured to compare the first current to a current required to perform a switching operation and output a value indicative of the leakage.

Abstract: An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.

Abstract: A network system may include a number of switches connected to a network processor that handles the bulk of the switching and/or routing in the system. The switches may provide per port flow control status information, e.g., the flow control status of a number of their ports, over a link to the network processor. The network processor may use this information to make traffic management decisions.

Abstract: Systems and techniques relating to managing a queue memory include, in some implementations, a method comprising: retrieving stored data from an oldest read entry in a FIFO queue memory having entries formed in hardware upon a first read operation; retrieving stored data from a selected entry in the FIFO queue memory upon a second read operation; and shifting data stored in entries of the FIFO queue memory with respect to the oldest read entry upon the first read operation and with respect to the specified entry upon the second read operation. In addition, some implementations include a queue memory comprising a hardware device having memory entries to receive and store data from a communications interface, wherein the queue memory supports first-in-first-out read operations and out-of-order read operations with data shifting among the entries of the memory relative to a read operation.

Abstract: A header analyzer unit generates attribute information regarding headers of a data unit. The header analyzer unit includes a programmable memory unit having a content addressable memory (CAM) with an input to receive a first portion of the data unit and a second portion of the data unit. The programmable memory unit also includes a memory separate from the CAM and coupled to an output of the CAM. The CAM stores indications of locations within the memory separate from the CAM, and the memory separate from the CAM programmably stores header attribute information regarding a plurality of different types of headers for data units having different formats.

Abstract: A search engine includes a storage module to store a plurality of data patterns, a plurality of busses to receive a plurality of representations of a search word, a selector corresponding to at least one of the plurality of data patterns to select one of the plurality of representations of the search word for comparing to the at least one of the plurality of data patterns, and a logic circuit operatively coupled to the storage module, to the plurality of busses, and to the selector to compare the selected one of the plurality of representations of the search word to the at least one of the plurality of data patterns.

Abstract: Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all, of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version.

Abstract: Apparatuses and methods are provided for generating a plurality of redundancy versions using various rate matching algorithms. In some embodiments, a rate matcher is provided that allocates systematic and parity bits to the redundancy versions in a manner that allows all of these bits to be transmitted in at least one redundancy version. In some embodiments, the rate matcher uses a first puncturing algorithm to generate both a first redundancy version and a third redundancy version, but allocates a different proportion of the systematic bits to these redundancy versions. In these embodiments, the second redundancy version may include only bits that were not transmitted in the first redundancy version.

Abstract: A logical load-balancing method for distributing traffic according to a set of weights among a group of network interfaces. A logical identity of a packet may be generated, e.g., by generating a hash index of the packet's header. Each of the weights may be associated with a network interface. A range of logical identities, or its boundary, may be determined for an interface according to the weight associated with the interface member. A packet may be directed to an interface if the packet's logical identify falls into the range of the interface.

Abstract: A system and method of managing data packets for transmission in a virtual network are disclosed. In some implementations, a network switch may generally comprise a packet modifier that modifies a VLAN tag state of a packet to be egressed as a function of an egress interface and a VLAN-ID assignment. The modified VLAN tag state may include one or more VLAN tags that are in a different order, or that have a different content, in comparison to the VLAN tags of the packet at the time of ingress.