Abstract: Low-noise magneto-resistive (MR) pre-amplifier circuit amplifies signal from MR head. MR head is biased at optimal point by current source to generate signal. Current source is powered by regulator to reduce noise contribution from Vcc due to finite output impedance of current source. Self-biased CMOS low-noise amplifier (LNA) minimizes input-referred noised without using negative power supply. Small MOS transistor with feedback tracking loop replaces self-bias resistor which determines lower corner cutoff frequency. This facilitates use of large-value resistor, thereby enabling on-chip integration of DC blocking input capacitor. Gm—Gm amplifier configuration increases gain bandwidth product and minimizes parasitic effects of MOS transistors.

Abstract: A variable gain amplifier includes a differentially-connected pair of NFETs for receiving differential input voltage signals. The source-drain channel of each NFET is coupled to a respective PFET operating in linear mode as a variable load resistance in a g.sub.m .times.R gain stage, the gain of which is determined by a gain-controlling signal applied to the gates of the PFETs. For broad dynamic range of voltage amplification, the drain of each NFET is coupled to a respective current source that is referenced to a supply voltage having a higher voltage level than the supply voltage for biasing the PFETs. Multiple stages of such variable gain stages are cascaded and independently gain controlled in successive stages to yield substantially exponential variation in overall gain as individual gain stages are adjusted. A control circuit controls the gains of each stage for obtaining a desired total overall gain for the multi-stage amplifier.

Abstract: A write driver for an inductive head of a magnetic storage medium that induces a faster write current switch across an inductive head element of a magnetic storage medium comprising having a pair of switches, S.sub.1 and S.sub.2, coupled to a pair of current sources, I.sub.1 and I.sub.2, wherein first switch S.sub.1 is coupled to first current source I.sub.1 and controlled by a first current switch control signal CLK. Second switch S.sub.2 is coupled to second current source I.sub.2 and controlled by second current switch control signal /CLK. First switch S.sub.1 is also controlled by first current control signal CLK to maximize rail to rail voltage swing. Similarly, second switch S.sub.2 is also controlled by second current control signal /CLK. In an alternative embodiment, a current booster is coupled to each current source to boost the write current to offset the otherwise decrease to write current due to damping resistor R.sub.

Abstract: A full flash analog to digital converter operates on an input voltage with a track/hold circuit coupled to a reference input of each of multiple comparators. Particular track/hold circuits are activated in sequence through a track/hold select circuit, and a look-up table and a digital-to-analog converter are coupled to supply corrected reference voltages to each track/hold circuit. Outputs of the comparators are supplied to a decoder which produces the digital output representative of the input voltage. The converter is calibrated before it is used for conversion by sensing the input offset voltages of each of the comparators and by altering the reference voltage for each comparator to produce a calibrated reference voltage for each comparator. A digital representation of the calibrated reference voltage for each comparator is stored in a look-up table for retrieval as needed to supply to a particular track/hold circuit a corresponding calibrated analog reference voltage for a particular comparator.

Abstract: Disclosed is a method for transient suppression in synchronous data protection systems which includes high-pass filtering of the signal produced by the sampling and shaping circuits before the signal enters the timing and gain control circuits. This high-pass filtering may be turned on when a transient is detected, in anticipation of a previously detected transient, or may be always on. Using the high-pass version of the shaped signal allows the timing loop and the gain loop to function during a transient interval, thus maintaining timing and gain lock during such an interval.

Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.

Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.