Abstract: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

Abstract: A massively parallel processor is provided with a plurality of clusters. Each cluster includes a plurality of processor elements ("PEs") and a cluster memory. Each PE of the cluster has associated with it an address register, a stage register, an error register, a PE enable flag, a memory flag, and a grant request flag. A cluster data bus and an error bus connects each of the stage registers and error registers of the cluster to the memory. The grant request flags of the cluster are interconnected by a polling network, which polls only one of the grant request flags at a time. In response to a signal on the polling network and the state of the associated memory flag, the grant request flag determines an I/O operation between the associated data register and the cluster memory over the cluster data bus. Both data and error bits are associated with respective processor elements. The sequential memory operations proceed in parallel with parallel processor operations.

Abstract: A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an array of processing elements or PEs (12.sub.1 -12.sub.N) that process respective sets of data according to instructions supplied from a global control unit (20). Each instruction is furnished simultaneously to all the PEs. One local control feature (52) entails selectively inverting certain instruction signals according to a data-dependent signal. Another local control feature (48) involves controlling the amount of a bit shift in a barrel shifter (98) according to a data-dependent signal.

Abstract: A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled.

Abstract: A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled.

Abstract: A network and method for interconnecting a plurality of router elements in a parallel computer. The network forms a routing system for routing data from source processing elements to destination processing elements. The input lines and output lines of each router chip are prioritized. Higher priority output lines from a given output group of a first routing element are connected to low priority input lines of a second routing element and lower priority output lines from the output group of the first rotating element are connected to higher priority input lines of the second routing element.

Abstract: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

Abstract: A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.