Abstract: A computer memory control capable of controlling a virtual memory system and optimized for handling multi-tasking or multi-processing systems is disclosed. In operation, each task or process is assigned a unique process number. The memory control circuitry which translates a virtual address produced by the system processor into a physical address suitable for memory access includes a unique translation buffer store each entry of which comprises a physical address, the usual tag bits and the process number of the process utilizing that address. During an address translation, buffer store entries are indexed using the virtual address used by the processor. In addition to the usual tag bit comparison to verify data validity, a comparison is made between the process number of the process presently running and the process number stored at the indexed buffer entry. The translation is considered successful only if both the tag bits and the process numbers match.