Abstract: A receiver (1) has an equalizer (2, 4, 5) which introduces inter symbol interferance (ISI) in a controlled manner and low pass filters to reduce noise. The ISI is introduced and the noise is reduced by a filter (4) in an adaptation path. A trellis decoder (3) of the receiver (1) removes the ISI to avoid propagation error. It does this in front end modules (20), outside of its critical path. There is a better decoder performance because noise is smaller.

Abstract: A Gigabit transceiver (1) has a receiver (2) and a transmitter (3). There is an ADC (5) in the receiver (2) for each channel (A, B, C, D). The ADCs (5) oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs (2) operate off half of the oversampling rate. In the receiver (2) fractionally spaced equalisers (FSES, 6) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

Abstract: A data communication receiver comprises an equalizer for adapting to each of a plurality of channels to open the eye for each channel in a Gigabit (1000BASE-T) transceiver. The eye is open for a first channel (A) and a transformation process applies the coefficients of that adaptation to open the eye for the other dimensions. The transformation process keeps the magnitude response constant.

Abstract: A cancellation system comprises a channel circuit (11) for each noise source, such as echo in a particular cable pair. There are only eighty taps per channel, in two blocks (n_echo_a, f_echo_a). Each block is preceded by a variable delay line comprising blocks of registers cascaded so that a delay value of 0 to 40 clock cycles can be chosen. The delay value is determined by determining an optimum position for each tap block. This is achieved by determining a maximum coefficient sum for a number of windows. Taps from other channels are used during training, so that there is a total of 160 taps for each channel during training to enable the optimum positions to be determined.

Abstract: An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU (3) has a register file (4) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) (5) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU (5), selection multiplexers (13, 14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the least significant bits (LSBs) are taken from the output of a second adder (adder2) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder.