Abstract: A wireless IC interconnect system and a source synchronous CDMA (SS-CDMA) bus interface facilitate interconnections between first and second IC locations. A signal conveyed using the wireless system is modulated and capacitively coupled to a transmission medium, and then capacitively coupled from the medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. Multiple signals can be conveyed simultaneously by modulating and demodulating them using multiple access algorithms such as CDMA and/or FDMA. The SS-CDMA bus interface utilizes source synchronous signaling and CDMA techniques to provide high bus concurrency and low channel latency. The interface is re-configurable, and provides multi-chip access in high-bandwidth multi-drop parallel interconnection applications.

Abstract: A wireless IC interconnect system and method facilitates interconnections between first and second IC locations via a wireless transmission medium; the IC locations may be on the same chip or on separate chips. A signal to be conveyed is modulated, and the modulated signal is capacitively coupled to the wireless transmission medium—preferably a properly terminated microstrip transmission line (MTL) or a coplanar waveguide (CPW). The modulated signal is capacitively coupled from the wireless medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. In a preferred embodiment, the wireless transmission system conveys numerous signals simultaneously, with the signals modulated and demodulated with multiple access algorithms such as code-division (CDMA) and/or frequency-division (FDMA) multiple access algorithms.

Abstract: A wireless IC interconnect system and a source synchronous CDMA (SS-CDMA) bus interface facilitate interconnections between first and second IC locations. A signal conveyed using the wireless system is modulated and capacitively coupled to a transmission medium, and then capacitively coupled from the medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. Multiple signals can be conveyed simultaneously by modulating and demodulating them using multiple access algorithms such as CDMA and/or FDMA. The SS-CDMA bus interface utilizes source synchronous signaling and CDMA techniques to provide high bus concurrency and low channel latency. The interface is re-configurable, and provides multi-chip access in high-bandwidth multi-drop parallel interconnection applications.

Abstract: A wireless IC interconnect system and method facilitates interconnections between first and second IC locations via a wireless transmission medium; the IC locations may be on the same chip or on separate chips. A signal to be conveyed is modulated, and the modulated signal is capacitively coupled to the wireless transmission medium—preferably a properly terminated microstrip transmission line (MTL) or a coplanar waveguide (CPW). The modulated signal is capacitively coupled from the wireless medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. In a preferred embodiment, the wireless transmission system conveys numerous signals simultaneously, with the signals modulated and demodulated with multiple access algorithms such as code-division (CDMA) and/or frequency-division (FDMA) multiple access algorithms.