Abstract: A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.

Abstract: A method for ramping a high-speed clock to control power surge in an integrated circuit when transitioning from a low power holdstate to an operational state where the integrated circuit includes selected logic circuits adapted to be maintained in the holdstate. A core clock signal including a plurality of core clock pulses is gated with a ramping signal. The ramping signal includes a series of staged signals having gating pulses. Each staged signal is separated by a ramp interval, where the series of staged signals successively enables increasing numbers of clocking pulses from the core clock signal to be transmitted to a holdstate output until a predetermined operational core clock frequency is transmitted to the holdstate output bringing the integrated circuit to the operational state.

Abstract: A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects.

Abstract: A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

Abstract: A method and apparatus are provided for aligning data in a binary word. A coded address is provided for each bit of the binary word. Each coded address is modified as a function of a logic state of the respective bit of the binary word to produce respective modified addresses. A shift control word is generated based on bit positions at which the modified addresses have a predetermined logic state. Bits in the binary word are shifted as a function of the shift control word to produce an aligned binary word.

Abstract: An integrated circuit layout pattern is formed from a plurality of objects placed within the layout pattern. Each object has a homogenous communications interface, which is a rectilinear donut structure formed of communications elements surrounding a central object logic area. The communications elements are adapted to route data between the central object logic area and other rectilinear donut structures in the layout pattern.

Abstract: A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

Abstract: A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

Abstract: A method and apparatus are provided for multiplying a multiplicand by a multiplier. The method and apparatus generate a plurality of partial products. Each partial product has a plurality of bits having respective binary weights, wherein each bit can have a first or second logic state. A first set of multiple-bit columns is formed from bits of the plurality of partial products, wherein the bits in each column of the first set have the same binary weight. Each multiple-bit column in the first set is encoded into a respective modified partial product, which represents a number of bits in the column having the first logic state. This process can be repeated until the number of partial products is reduces to a desired number.

Abstract: A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

Abstract: A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.