Abstract: A method and system for enabling a designer to more easily convert a model of a dynamic system instantiated using floating-point representation such as has been created in a high level design language to fixed-point code suitable for execution in a programmable processor or logic array.

Abstract: A system and method evaluates power information for a high-level model to be implemented in target hardware, and performs one or more power-reducing transmutations on the model. Transmutations may include moving one or more components from a fast rate region to a slow rate region, reducing bit width of data, signals, or other values, and replacing multiple instances of a resource with a shared instance of the resource. An in-memory representation of the model may be generated that reduces the model to a plurality of core components. A power score evaluation engine may assign power scores to the core components. Power scores may be retrieved from one or more power score database. The power scores may be non-dimensional scores representing power consumption relationships among the core components, and be target independent. Hints or alerts regarding suggested changes to the model to optimize power consumption may be presented to a user. A revised model incorporating the suggested changes may be constructed.

Abstract: A system and method introduces one or more errors into computer programming code generated from a model or other source program. The one or more errors are not present in the model, but are introduced into the code generated from the model. The one or more errors may simulate one or more bugs in the code generation process. The generated code, including the one or more introduced errors, may be analyzed by one or more verification tools. The one or more verification tools examine the generated code in an effort to detect the one or more errors that were introduced. The one or more verification tools may compare the generated code to the model or source program. If the one or more verification tools is able to detect the one or more introduced errors, then the one or more verification tools may be considered to be validated.

Abstract: A system generates a simplified model from an original model, where the simplified model exhibits the same error or undesired behavior as the original model but is smaller. A condition may be defined that, when evaluated, may determine whether the error or undesired behavior occurs in a model. A search engine may identify one or more portions of the original model as candidates for deletion. A series of intermediate models of decreasing size may be constructed by deleting selected ones of the candidate portions, provided that the intermediate models also produce the same error or undesired behavior. The system may continue an iterative process until it resolves to the simplified model, and the simplified model may be analyzed to locate the source or cause of the error or undesired behavior.

Abstract: The present invention provides a method and system for automatic verification of automatically generated standalone code intended for execution on a target computing platform against its original design simulated in a simulation environment. The present invention also applies to execution comparisons between two implementations, such as two simulations, one simulation and one standalone code implementation, or two standalone code implementations. Block diagrams can be used to create a comparison model that compares two implementations. The comparison of different implementations can be performed at a block level, a subsystem level, a model level, or multi-model level. The present invention allows automatic comparison once a user supplies the intermediate outputs and/or signals that the user wants to compare and monitor. Reports can be generated to show the statistics of the comparison results.

Abstract: A system and method may generate executable block diagrams having blocks that run in accordance with message-based execution semantics. A message may include an input data payload that does not change over time, and the message may persist for only a determined time interval during execution of block diagram. A verification engine may provide one or more tools for evaluating and verifying operation of message-based blocks. The verification engine may support one or more verification blocks that may be added to the block diagram and associated with the diagram's message-based blocks. The verification blocks may capture and present messages exchanged among the message-based blocks. The verification blocks may also specify an expected interaction of messages, and determine whether the actual messages are equivalent to the expected interaction.

Abstract: A method includes performing an analysis or synthesis operation on a graphical model representation, producing a report from the analysis or synthesis operation and generating associations representing elements of the graphical model representation with corresponding elements in the report and using these associations as a way to reposition viewer based on actions to the graphical model representation.

Abstract: A device receives model information associated with a modeling application. The device determines first and second conflicting information in the model information. The first and second conflicting information describe different characteristics of a model described by the model information. The device formats the first and second conflicting information in a manner that designates the first conflicting information as a first variant of the model and the second conflicting information as a second variant of the model. The model, when executed with the first variant, behaves in a different manner than when executed with the second variant. The device provides the formatted first and second conflicting information to the modeling application, provides information that identifies the first and second variant, receives a user selection of information that identifies the first variant or second variant, and executes the model based on the user selection.

Abstract: A system and method graphically display ports in a discrete event system (DES) environment. A graphical representation of a model having at least one DES component is provided in the DES environment. A first port of the DES component and a second port of the DES component are indicated by symbols. The first port is indicated by a first symbol representing a port type of the DES environment and the second port is indicated by a second symbol representing a port type of a non-DES environment.

Abstract: A method of preventing interference between subsystem blocks includes obtaining an integrity level for a first subsystem block, obtaining an integrity level for a second subsystem block, assigning an integrity level property to at least one input port of the first block, the integrity level property assigned to the input port of the first block being based on the integrity level defined for the first block, and assigning an integrity level property to at least one output port of the second block, the integrity level property assigned to the output port of the second block being based on the integrity level defined for the second block. The method further includes evaluating the integrity level property of at least one input/output pair to determine whether an inappropriate connection exists, and performing a first action when an inappropriate connection exists, or performing a second action when an appropriate connection exists.

Abstract: A method of integrating freehand user input into a block diagram environment is disclosed. The freehand user input is a user's approximation of a diagram component or feature of a component which is received by the block diagram environment and compared to multiple patterns stored in a storage location. The storage location holds patterns of block diagram components and block diagram component features. The freehand user input may be displayed, superimposed on a block diagram being shown to the user. Upon the freehand user input being matched to one of the patterns representing a block diagram component or feature of a component, the freehand user input is replaced on the displayed block diagram with an electronic device drawn rendering of the matched diagram feature component or feature of a component. Partial matches of the user drawn input may result in a menu of choices being presented to the user for selection.

Abstract: A device receives code generated via a technical computing environment (TCE), where the code includes one or more values to be tested. The device receives Boolean constraints and diagnostic information, and generates a test based on the Boolean constraints and the diagnostic information. The device performs the test on the one or more values of the code to generate a result, and outputs or stores the result.

Abstract: A system and method automatically ensures consistency among a design model and one or more test models that test the design model. The system may include a broker adapted to construct an interface specification. The interface specification identifies the interface of the design model, e.g., its external inputs, external outputs, and initialization states. It may also identify the outputs, inputs, and initialization setting objects of the test models. Proposed changes to the design model's interface may be captured by the broker, and applied to the design model and to the test models atomically. Proposed changes to a given test model that implicate the design model's interface also may be captured, and applied to the given test model, the other test models, and the design model atomically. Default behaviors may be defined for applying the proposed changes to the other test models and the design model.

Abstract: A device receives a model that includes model elements scheduled to execute in time slots on a hardware device. The device identifies time slots, of the time slots, that are unoccupied or underutilized by the model elements, and identifies a set of model elements that can be moved to the unoccupied time slots without affecting a behavior of the model. The device calculates a combined execution time of the model elements, determines whether the combined execution time of the model elements is less than or equal to a duration of a first time slot of the time slots, and schedules the model elements for execution in the first time slot when the combined execution time of the model elements is less than or equal to the duration of the first time slot.

Abstract: A system obtains code that includes sequences of code; identifies, within a first sequence of code and based on obtaining the code, a first routine that, when executed, enables an array of values to be generated. The array of values is associated with a variable included within the first routine. The system determines whether the routine includes a particular term, and identifies, within the routine, a first identifier when the routine includes the particular term. The first identifier corresponds to a second sequence of code that identifies a first data structure that stores information that identifies one or more second routines. The system identifies, within the data structure, a second routine based on the particular term and a second identifier corresponding to the first routine; executes, using the variable, the second routine to generate a result; and outputs the result based on executing the second routine.

Abstract: A system obtains first code that includes one or more lines of code, the lines of code including first information associated with one or more data types or one or more routine types. The system removes the first information from the lines of code; and generates one or more instructions that, when executed, enable the system to obtain the first information or second information. The second information is associated with at least one data type that is different than the one or more data types or at least one routine type that is different than the one or more routine types. The system modifies the lines of code based on the one or more instructions; generates second code based on the first code and the modified lines of code; and outputs the second code.

Abstract: Exemplary embodiments support multi-threaded subgraph execution control within a graphical modeling or graphical programming environment. In an embodiment, a subgraph may be identified as a subset of blocks within a graphical model, or graphical program, or both. A subgraph initiator may explicitly execute the subgraph while maintaining data dependencies within the subgraph. Explicit signatures may be defined for the subgraph initiator and the subgraph either graphically or textually. Execution control may be branched wherein the data dependencies within the subgraph are maintained. Execution control may be joined together wherein the data dependencies within the subgraph are maintained. Exemplary embodiments may allow subgraphs to execute on different threads within a graphical modeling or programming environment.

Abstract: One or more computer-readable storage media for storing computer-executable instructions executable by processing logic is provided. The media storing one or more instructions that when executed by the processing logic causes the processing logic to receive data in a first format for conversion to a second format different than the first format, wherein the data includes information having a first type and information having a second type and display the data in the first format via a graphical interface. One or more translation rules are received relating to processing the information having the first type or the information having the second type. The one or more translation rules are pre-applied to the data in the first format. Effects of the pre-applied rules on the displayed data are displayed via the graphical interface. The data in the first format is converted to the data in the second format based on the one or more translation rules.

Abstract: A computer-readable memory device may include instructions to store data describing a state machine model including source states and destination states. The device may also include instructions to store, for each of the source states, a condition field identifying a condition upon which, when satisfied, the state machine model transitions from the source state to one of the destination states. The device may also include instructions to store, for each of source states, a destination field identifying the one of the destination states. Each of at least two of the source states may identify an identical destination state in the corresponding destination field. Each of at least two of the source states may identify an identical condition in the corresponding condition field.

Abstract: A computing device may include a memory to store data that describes a state machine model that includes destination states and source states. The source states may be associated with conditions upon which the state machine model is to transition from a corresponding source state to one of the destination states. The device may also include a processor configured to generate data to describe a state diagram from the data that describes the state machine model. The state diagram may include the graphical symbols and lines. Each of the graphical symbols may represent one of the source states or one of the destination states. The lines may represent transitions and include one or more vertical lines to represent transitions to one of the destination states from more than one of the source states. The graphical symbol may represent the one of the destination states is not adjacent to the graphical symbols to represent the more than one of the source states.