Abstract: A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.

Abstract: A line amplifier for static RAM memory in CMOS technology comprises first and second branches formed by a first plurality of transistors (TP.sub.1, TN.sub.1, TN.sub.2) and a second plurality of transistors (TP.sub.2, TN.sub.3, TN.sub.2), respectively. The branches are connected in series between the power supply (Vdd) and reference voltage (Vss). A positive feedback is produced by direct connection through internal nodes, and an evaluation switching transistor makes it possible to equalize the values of the voltages on the internal nodes at equilibrium. Under read control (CL), the transistor (TN.sub.2) makes it possible to amplify the preliminary difference between voltage levels due to a transition of the bit signal (D) and complemented bit signal (D) applied to the internal nodes. A precharge transistor (TN.sub.4) is common to the first and second branches and thus allows an increase in switching speed.

Abstract: An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.

Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: A three-state output interfacing device for a CMOS memory that comprises a stage for selective control of the device, receiving an input signal (I) at the bit frequency and a control signal (e) and making it possible to deliver, on two ports (A) and (B), either complemented signals (I), or distinct logic levels for driving the device into the high-impedance state, a first inverter stage delivering first inverted logic signals, from the ports (A) and (B), on two ports (C) and (D), a second inverter stage delivering second inverted signals from the ports (C) and (D), a stage for reducing the analog difference between the second inverted signals and for switching the output interfacing device into high-impedance state at ports (E) and (F), and an output stage receiving the signals from the ports (E) and (F) after reduction of analog difference and making it possible to fix and balance the current for charging and discharging the output capacitance of the output interfacing device and its high-impedance switching

Abstract: A method of fabricating a read only memory consisting of a matrix of arrays of enhancement-mode or depletion-mode programmed MOS transistors that consists, on a silicon substrate (SU) of a first conduction type, in defining by masking, retrograde wells of the same conduction type as that of the substrate, and then retrograde wells of conduction type opposite to that of the substrate. Removal of the protective oxide allows thus to predefine the enhancement-mode and depletion-mode transistors.

Abstract: A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.

Abstract: A transition detection device, generating a variable-duration pulse, such as an enable signal for the input circuits of a CMOS static memory circuit, receiving an input signal that includes a delay circuit of determined delay value, making it possible to generate a delayed enable signal, with a safety margin of duration equal to the delay value. A calibration circuit is provided, which includes an exclusive-OR circuit receiving the input signal on a first input. A controlled delay circuit is provided to deliver an input signal delayed by a second delay value to a second input of the exclusive-OR circuit, which, upon access by the CEB signal, delivers a calibrated output pulse of duration equal to the second delay value, and truncated pulses for any transition occurring on the other inputs of the circuit, in the presence of address transitions or of other, not strictly simultaneous, inputs.

Abstract: A comparator of phase between a digital signal and a clock signal adapted for the construction of a phase locked loop in integrated circuit form, that includes a first channel formed by a flip-flop and an exclusive OR gate, and a second channel formed by a second exclusive OR gate and a delay circuit whose delay is set to half the period of the clock signal. The first channel receives the digital signal and the clock signal and delivers a first detection signal of transition of the digital signal. The second channel receives only the digital signal and delivers a second detection signal of transition of the digital signal.

Abstract: An output circuit for a TTL-CMOS integrated circuit that comprises an output stage with two P MOS and N MOS transistors in parallel, which are connected in cascade with an N MOS enabling transistor between the power supply and the reference voltages. The output stage connected by means of a validation signal TRISB and of P and N MOS transistors delivers an output signal representing the input logic variable to the common point between the P MOS transistor and enabling transistor. A first circuit allows switching of the P MOS transistor by an intermediate switching control signal TRISP and a third circuit allows switching of the N MOS transistor, the circuit operating in mode of feedback of the switching control of the P MOS transistor, the controls being applied successively in order to generate an intermediate switching level belonging to the high logic level.

Abstract: A device for monitoring the boron content of the borophosphosilicate, BPSG. The BPSG is obtained by the oxidation of silane, of diborane and of phosphine in a reactor, starting with a first, diborane/silane gas mixture and a second, phosphine/silane gas mixture by monitoring the ratio .rho.=diborane/(diborane+silane) of the mixture resulting from the mixing of the first and second gas mixtures. Monitoring of the boron content is obtained by measuring the density of the first mixture, determining the amount of residual hydrogen in the first mixture and modulating the mass flow rate of the first mixture in response to the calculated ratio .rho..

Abstract: A method for monitoring the boron content of the borophosphosilicate, BPSG. The BPSG is obtained by the oxidation of silane, of diborane and of phosphine in a reactor, starting with a first, diborane/silane gas mixture and a second, phosphine/silane gas mixture by monitoring the ratio .rho.=diborane/(diborane+silane) of the mixture resulting from the mixing of the first and second gas mixtures. Monitoring of the boron content is obtained by measuring the density of the first mixture, determining the amount of residual hydrogen in the first mixture and modulating the mass flow rate of the first mixture in response to the calculated ratio .rho..

Abstract: The protection device comprises a MOS transistor formed on the substrate of the integrated circuit and connected between a circuit pad and a reference terminal of the integrated circuit. A thyristor formed on the substrate is connected between the pad and the reference terminal. The control electrode of this thyristor consists of a region of the substrate in such a way that the thyristor can be triggerred by a current of charge carriers produced in the substrate by avalanche when a voltage rise occurs between the substrate and the drain of the MOS transistor.

Abstract: The invention concerns a process for slope etching a layer of an integrated circuit. The layer to be etched is coated with a masking photoresist layer. The process consists of jointly performing a passivation of the etching flank of the layer to be etched and a nonisotropic erosion of the masking photoresist layer, which makes it possible to control the slope of the etching flank of the layer to be etched.

Abstract: A read protected semi-conductor program memory that can be used for protection of read-only memories built in microhandler of microcomputers comprising a first program memory area intended for storing the program data and a second encryption memory area intended for storing encryption data. A logical operator in intercoupled with the program and encryption memory areas making thus possible, on simultaneous reading of the program and encryption memory areas, to obtain encrypted program data.

Abstract: A TTL-CMOS output stage for an integrated circuit includes a bipolar transistor and a MOS transistor series connected between the power supply and ground, their common point forming the output terminal of the TTL-CMOS output stage. A first switching control input channel includes an inverter whose input forms the input terminal of the stage and whose output is connected to the gate of the MOS transistor via a resistor. A second switching control input channel includes a second inverter controlled by the first inverter and whose output is connected to the base of the bipolar transistor by means of a second resistor. The resistors make it possible to limit the transient current and the mean current supplied by the bipolar transistor.