Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Abstract: A method to laser anneal a silicon stack (or a silicon-rich alloy) including a heavily doped region buried beneath an undoped or lightly doped region is disclosed. By F selecting laser energy at a wavelength that tends to be transmitted by crystalline silicon and absorbed by amorphous silicon, crystallization progresses through the silicon layers in a manner that minimizes or prevents diffusion of dopants upward from the doped region to the undoped or lightly doped region. In preferred embodiments, the laser energy is pulsed, and a thermally conductive structure beneath the heavily doped layer dissipates heat, helping to control the anneal and limit dopant diffusion.

Abstract: In the present invention a dummy structure is formed in a first deposited layer in order to create topography, generally a raised area, in a deposited layer formed above and later than the first deposited layer. This topography may be advantageous in later steps. In one embodiment, transferred topography allows an alignment or overlay mark obscured by an opaque layer to be located by this enhanced topography. In another embodiment, a raised volume of dielectric material prevents features at the outside of an array area from being overpolished during a CMP step. This method may prove useful in other contexts as well. The size, shape, and placement of the dummy structure is tailored to form the desired excess volume.

Abstract: A layer of resistivity-switching metal oxide or nitride can attain at least two stable resistivity states. Such a layer may be used in a state-change element in a nonvolatile memory cell, storing its data state, for example a “0” or a “1”, in this resistivity state. Including additional metal atoms in a layer of such a resistivity-switching metal oxide or nitride compound decreases the current required to cause switching between resistivity states, reducing power requirements for an array of memory cells storing data in the resistivity state of such a layer. In various embodiments a memory cell may include a layer of resistivity-switching metal oxide or nitride compound with added metal formed in series with another element, such as a diode or a transistor.

Abstract: Use of antimony as an n-type conductivity-enhancing dopant in semiconductor structures having a vertical dopant profile is described. Dopants tend to diffuse, and steep dopant gradients can be difficult to maintain. Specifically, when a silicon layer is doped with phosphorus or arsenic, both n-type dopants, dopant atoms tend to seek the surface as undoped silicon is deposited on top of the n-doped layer, rising through the undoped silicon during deposition. Antimony does not have this tendency, and also diffuses more slowly than either phosphorus or arsenic, and this is advantageously used to dope such structures.

Abstract: A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.

Abstract: A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.

Abstract: Aspects of the present invention provide for a novel photomask for patterning features for an integrated circuit, the photomask including a first area transmitting light in a first phase surrounded by second area, the second area transmitting light in a second phase, the second phase opposite the first phase. No blocki. material separates the first area from the second area. After development of photoresist, the transition between the first and second area causes formation of a residual photoresist feature on the photoresist surface due to phase canceling of light. If the first area is small enough, it is nonprinting, ie., the opposite sides of the residual photoresist feature formed at its perimeter merge, forming a contiguous photoresist feature, and thus a corresponding patterned feature after etch.

Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Abstract: A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three-terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.

Abstract: A method of plasma etching comprises using a primary etchant of carbon monoxide gas to etch a transition metal or transition metal compound and to form a volatile by-product of metal carbonyl.

Abstract: A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.

Abstract: A memory array having memory cells each comprising a diode and a phase change material or antifuse is reliably programmed by maintaining all word lines and bit lines connected to unselected memory cells at intermediate voltages and applying voltages to place the diode of a selected cell or cells in a reverse biased state and sufficient to program the phase change material or antifuse. Thus leakage through unselected cells is low so power wasted is small, and assurance is high that no unselected memory cells are disturbed.

Abstract: A chemical vapor deposition method provides a smooth continuous germanium film layer, which is deposited on a metallic substrate at a sufficiently lower temperature to provide a germanium device suitable for use with temperature sensitive materials such as aluminum and copper. Another chemical vapor deposition method provides a smooth continuous silicon germanium film layer, which is deposited on a silicon dioxide substrate at a sufficiently low temperature to provide a germanium device suitable for use with temperature sensitive materials such as aluminum, copper and chalcogenides memory materials.

Abstract: A system and method of controlling a three dimensional memory is disclosed. In a particular embodiment, the system is implemented as an integrated circuit including a microcontroller having a control signal output, a three-dimensional monolithic non-volatile memory having a plurality of levels of memory cells above a silicon substrate and having an input responsive to the control signal output, a counter coupled to the microcontroller, and a program memory. The counter is to step through a series of time steps defining a program pulse time interval of a first program pulse to be applied to at least one selected memory cell within the three-dimensional monolithic non-volatile memory. The program memory is accessible to the microcontroller, and the program memory includes a sequence of program instructions corresponding to a memory operation with respect to the three-dimensional monolithic non-volatile memory.

Abstract: A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance-switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have either a vertically oriented channel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.

Abstract: A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.

Abstract: A memory cell is described suitable for use in a high-density monolithic three dimensional memory array. In preferred embodiments of the memory cell, a semiconductor junction diode formed of germanium or a germanium alloy which can be crystallized at relatively low temperature is formed disposed between conductors. The use of a low-temperature material allows the conductors to be formed of copper or aluminum, both low-resistivity materials that provide adequate current at very small feature size, allowing for a highly dense stacked array.

Abstract: In a novel rewriteable nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgOx, CrO2, VO, BN, and AlN. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors.

Abstract: In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.