Patents Assigned to Matsuhita Electronics Corporation
  • Patent number: 6300242
    Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: October 9, 2001
    Assignee: Matsuhita Electronics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobou Aoi, Hideo Nakagawa