Patents Assigned to Matsushita Electronics Corp.
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Patent number: 6653714Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills thType: GrantFiled: November 20, 2002Date of Patent: November 25, 2003Assignee: Matsushita Electronics Corp.Inventors: Toshinobu Matsuno, Takeshi Fukuda, Katsunori Nishii, Kaoru Inoue, Daisuke Ueda
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Patent number: 6420743Abstract: Object: In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed. Measure to Solve: Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2.Type: GrantFiled: August 11, 2000Date of Patent: July 16, 2002Assignee: Matsushita Electronics, Corp.Inventors: Hiroshige Hirano, Masato Takeo
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Patent number: 6396508Abstract: There is provided a method and system for improving an image on a display that images pixels. Each of the pixels has an intensity represented by a respective pixel value, an intensity of a given pixel being associated with a number of pulses produced within a set of subfields in a frame-time, and the pulses allocated among the set of subfields in accordance with a pulse distribution. The method comprises the steps of determining a maximum pixel value to be imaged during the frame-time, and altering a number of pulses within a given subfield based on the maximum pixel value, thus modifying the pulse distribution. The system is implemented in a circuit that executes the method steps.Type: GrantFiled: December 2, 1999Date of Patent: May 28, 2002Assignee: Matsushita Electronics Corp.Inventor: James D. Noecker
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Patent number: 6265327Abstract: Disclosed are a method and apparatus for forming an insulating film on the surface of a semiconductor substrate capable of improving the quality and electrical properties of the insulating film with no employment of high-temperature heating and with good controllability. After the surface of a silicon substrate is cleaned, a silicon dioxide film having a thickness of 1-20 nm is formed on the substrate surface. The silicon substrate is exposed to plasma generated by electron impact, while the silicon substrate is maintained at a temperature of 0° C. to 700° C. Thus, nitrogen atoms are incorporated into the silicon dioxide film, obtaining a modified insulating film having good electrical properties.Type: GrantFiled: June 17, 1998Date of Patent: July 24, 2001Assignees: Japan Science and Technology Corp., Matsushita Electronics Corp.Inventors: Hikaru Kobayashi, Kenji Yoneda
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Patent number: 6229150Abstract: A group III-nitride quatenary material system and method is disclosed for use in semiconductor structures, including laser diodes, transistors, and photodetectors, which reduces or eliminates phase separation and provides increased emission efficiency and reliability. In an exemplary embodiment the semiconductor structure includes first GaAINAs layer of a first conduction type formed substantially without phase separation, an GaAINAs active layer substantially without phase separation, and a third GaAINAs layer of an opposite conduction type formed substantially without phase separation.Type: GrantFiled: July 30, 1999Date of Patent: May 8, 2001Assignee: Matsushita Electronics Corp.Inventors: Toru Takayama, Takaaki Baba, James S. Harris, Jr.
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Patent number: 6163043Abstract: In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed. Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2.Type: GrantFiled: April 6, 1998Date of Patent: December 19, 2000Assignee: Matsushita Electronics Corp.Inventors: Hiroshige Hirano, Masato Takeo
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Patent number: 6081036Abstract: A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.Type: GrantFiled: March 9, 1998Date of Patent: June 27, 2000Assignee: Matsushita Electronics Corp.Inventors: Hiroshige Hirano, Toshiyuki Honda
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Patent number: 6025632Abstract: A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor.Type: GrantFiled: December 11, 1997Date of Patent: February 15, 2000Assignee: Matsushita Electronics Corp.Inventors: Takeshi Fukuda, Hiroshi Takenaka, Hidetoshi Furukawa, Takeshi Fukui, Daisuke Ueda
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Patent number: 5821625Abstract: The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: April 23, 1996Date of Patent: October 13, 1998Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga
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Patent number: 5767009Abstract: The present invention reduces crosstalk noise, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip (1) having a first electrode pad (2) and a first wiring layer (9), and a second semiconductor chip (5) having a second electrode pad (6) and a second wiring layer (10). A bump (4) is provided for electrically coupling the first electrode pad (2) and the second electrode pad (6). An insulation layer 8 is disposed between confronting surfaces of the first semiconductor chip (1) and the second semiconductor chip (5). An electro-conductive layer (7) is disposed between the confronting surfaces of the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: February 10, 1997Date of Patent: June 16, 1998Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga
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Patent number: 5514888Abstract: A first P-type diffusion layer is formed on a semiconductor substrate. A photodiode is formed thereon. A transfer channel is formed on the semiconductor substrate. Agate insulating film is grown from a silicon oxide film on the semiconductor substrate. A transfer gate electrode is formed on the gate insulating film by patterning polysilicon. A light-shielding film of a metallic evaporation film is formed on the transfer gate electrode so that light cannot enter the transmission channel only to be a smear component. A difference in level of about 2 to 4 .mu.m is formed on the semiconductor substrate of the transfer channel due to the transfer gate electrode and the light-shielding film. An underlying smooth layer is formed to smooth the surface difference in level, and a first light-shielding layer is formed on it. A transparent film is formed on it, and a third light-shielding layer is formed via a second light-shielding layer and a transparent film.Type: GrantFiled: May 24, 1993Date of Patent: May 7, 1996Assignee: Matsushita Electronics Corp.Inventors: Yoshikazu Sano, Hiroshi Okamoto
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Patent number: 5466612Abstract: A dielectric film is formed on a P type silicon substrate. Then a specified resist pattern is formed on the dielectric film. Using this resist pattern as the mask, a phosphorus ion beam is implanted. Then, removing the resist pattern, heat treatment is given. By this heat treatment, a photo diode is formed in a depth of about 1 .mu.m. A specified resist pattern is formed again on the dielectric film. Using this resist pattern as the mask, boron ions are implanted. Thus, a channel stopper region is formed. Afterwards, removing the resist pattern, the dielectric film is removed. Again, a dielectric film is formed on the silicon substrate. Later, a stacked oxide film is formed in the other regions than the region for forming the photo diode on the dielectric film. Using the stacked oxide film as the mask, a boron ion beam is implanted.Type: GrantFiled: June 24, 1993Date of Patent: November 14, 1995Assignee: Matsushita Electronics Corp.Inventors: Genshu Fuse, Katuya Ishikawa
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Patent number: 4734686Abstract: A gas discharge display apparatus consisting of a gas discharge display panel and a drive circuit for driving a matrix array of display elements formed in the display panel by mutually perpendicular arrays of stripe-shaped anodes and cathodes, the cathodes being sequentially selected during successive scanning intervals and the anodes driven to produce a light-emitting or non-emitting state during each scanning interval in accordance with display data. During each scanning interval, each anode for which the non-emitting state is to be maintained is momentarily driven to the light-emitting state potential during a brief interval, to thereby substantially increase the reliability of display operation during the immediately succeeding scanning interval.Type: GrantFiled: November 20, 1986Date of Patent: March 29, 1988Assignee: Matsushita Electronics Corp.Inventors: Takio Okamoto, Ryoji Inutsuka, Yukiharu Ito
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Patent number: 4600858Abstract: In a cathode ray tube apparatus having an in-line type electron gun, magnetic pole pieces comprising four pole pieces of substantially arc-shaped cross section are disposed in a cylindrical shape with circumferential gaps between neighboring pole pieces 0.degree., 90.degree., 180.degree., and 270.degree. locations on the cylinder. An additional pair of narrow width stripe-shaped pole pieces are disposed inside said cylinder at a predetermined distance from the cylinder in a manner to cover the 90.degree. and 180.degree. gaps. The apparatus acting to modify the horizontal and vertical deflection magnetic fields so that the electron beam spots on the phosphor CRT screen are substantially circular in shape without losing the self convergence effect of the magnetic fields.Type: GrantFiled: May 10, 1984Date of Patent: July 15, 1986Assignee: Matsushita Electronics Corp.Inventors: Katsuyo Iwasaki, Osamu Konosu, Atsushi Kihara, Masayasu Kamada
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Patent number: 4482915Abstract: The invention provides a lead frame for a plastic encapsulated semiconductor device wherein one of the external leads connected to a first connecting band extends from one edge of a substrate support which supports a semiconductor substrate and also serves as a heat sink, two strips are connected to a second connecting band from the other edge of the substrate support, a notch is formed between the two strips of the second connecting band to allow proper positioning of the lead frame and to decrease thermal deformation during plastic encapsulation. Further, another lead frame is provided wherein a through hole is formed extending within the substrate support in the direction of thickness thereof in order to allow uniform flow of the resin and to form a thin resin layer on the rear surface of the substrate support.Type: GrantFiled: July 6, 1982Date of Patent: November 13, 1984Assignee: Matsushita Electronics Corp.Inventors: Mikio Nishikawa, Hiroyuki Fujii, Kenichi Tateno, Masami Yokozawa
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Patent number: 4392154Abstract: A solid-state color image sensor in which a photosensor region comprises a plurality of parallel transfer electrodes and a plurality of channel stops extended at right angles to the transfer electrodes; the photosensor region is divided into a plurality of elements each comprising a predetermined number of transfer electrodes; one of the transfer electrodes of each element which are adjacent to other elements is optically shielded; and voltages are applied to the transfer electrodes of each element in such a way that the potentials below the optically shielded transfer electrode, the transfer electrode or electrodes which do not collect signal charges, the channel stop and the transfer electrode or electrodes which collect the signal charges become progressively deeper in the order named. Mixtures of the signal charges from the different color picture elements can be avoided, so that an image with a higher degree of color purity can be obtained.Type: GrantFiled: June 10, 1981Date of Patent: July 5, 1983Assignee: Matsushita Electronics Corp.Inventor: Kenju Horii
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Patent number: 4366503Abstract: A solid-state image pick-up device has transfer gates and storage capacitive elements with smaller capacitance than that of a vertical transfer lines between the vertical transfer lines to which signal charge is transferred through the operation of a signal charge transfer circuit containing the vertical shift register and switch elements, and a horizontal shift register for receiving the signal charge. The horizontal shift register is of the charge coupling type. The horizontal shift register has unit elements two times the vertical transfer lines. An optical signal and the other charge than the optical signal charge are stored in the adjacent unit elements and then the other charge than the optical charge is outputted to the other portion than a signal output portion.Type: GrantFiled: October 15, 1980Date of Patent: December 28, 1982Assignees: Matsushita Electronics Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Sumio Terakawa, Tohru Takamura, Kenju Horii, Takahiro Yamada
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Patent number: D353902Type: GrantFiled: January 14, 1994Date of Patent: December 27, 1994Assignee: Matsushita Electronics Corp.Inventors: Masashi Sangen, Takeshi Matsumura, Shiro Iida