Abstract: An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract: A semiconductor structure is provided. An N-type epitaxial layer is disposed on an N-type substrate. The N-type epitaxial layer has at least one trench therein, wherein the trench has a straight sidewall. A first insulating layer is disposed on at least a portion of a surface of the trench. A silicon-containing layer is disposed in a lower portion of the trench and has at least one air gap therein. A first conductive layer is disposed in an upper portion of the trench. Two P-type well regions are disposed in the N-type epitaxial layer beside the trench. Two N-type source regions are respectively disposed in the P-type well regions beside the trench.

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

Abstract: Provided is a light sensor including a substrate, a dielectric layer, a plurality of pixels, a plurality of spacers, and a plurality of metal interconnects. The dielectric layer is located on the substrate. The pixels are located in the dielectric layer. The spacers are located on the sidewall of openings between adjacent pixels. The metal interconnects are located in the openings and cover the spacers so as to be electrically connected to the corresponding pixels.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell and periphery areas. A patterning step is performed to form first and second stacked structures on the substrate respectively in the cell and periphery areas. First and second spacers are formed respectively on sidewalls of the first and second stacked structures. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure.

Abstract: Provided is a multi-wave band light sensor combined with a function of infrared ray (IR) sensing including a substrate, an IR sensing structure, a dielectric layer, and a multi-wave band light sensing structure. The substrate includes a first region and a second region. The IR sensing structure is in the substrate for sensing IR. The dielectric layer is on the IR sensing structure. The multi-wave band light sensing structure includes a first wave band light sensor, a second wave band light sensor, and a third wave band light sensor. The second wave band light sensor and the first wave band light sensor are overlapped and disposed on the IR sensing structure on the first region of the substrate from the bottom up. The third wave band light sensor is in the dielectric layer of the second region.

Abstract: An ambit light sensor with a function of IR sensing and a method of fabricating the same are provided. The ambit light sensor includes a substrate, an ambit light sensing structure, an infrared ray (IR) sensing structure, and a dielectric layer. The ambit light sensing structure is located over the substrate for sensing and filtering visible light. The IR sensing structure is located in the substrate under the ambit light sensing structure for sensing IR. The dielectric layer is located between the ambit light sensing structure and the IR sensing structure.

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region.

Abstract: A check valve includes a case body, a piston device, and a blocking plate. The case body includes a first case part and a second case part. The first case part has a first opening. The second case part has a second opening and a third opening. The second opening faces the first opening, and the third opening is located at one side of the second opening. The first case part and the second case part are combined to form the case body, and the case body has a fluid passage therein. The piston device is aligned to the second opening and mounted on the second case part. The blocking plate is disposed on the piston device. When the piston device operates, the piston device pushes the blocking plate to seal the first opening.

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.

Abstract: A method of measuring a numerical aperture of an exposure machine is described. A control wafer having vernier marks thereon and an aberration mask having pinholes therein are provided, wherein each pinhole corresponds to a vernier mark in position. A lithography process using the exposure machine and the aberration mask is performed to the control wafer, so as to form over each vernier mark a photoresist pattern having the same shape of the illumination pattern of the light source of the exposure machine. The numerical aperture of the exposure machine is then derived from a graduation of the vernier mark corresponding to an outer edge of the photoresist pattern.

Abstract: A one time programmable memory having a memory cell formed on a substrate is provided. The memory cell has a transistor and an anti-fuse structure. The anti-fuse structure is consisted of a doping region, and a dielectric layer and a conductive layer is formed in the top edge corner region of an isolation structure. The upper surface of the isolation structure is lower than the surface of the substrate so as to expose the top edge corner region. The conductive layer is formed on the isolation structure and covers the top edge corner region. The dielectric layer is formed on the top edge corner region and between the doping region and the conductive layer. The memory cell stores the digital data depending on whether the dielectric layer breaks down or not.