Patents Assigned to MAXELER TECHNOLOGIES LTD.
  • Patent number: 9584594
    Abstract: A system and method of dynamically provisioning virtualized computational resources in a networked computer architecture includes at least one client device operable to run one or more client applications, at least one server device and a resource controller. Each server device comprises one or more physical processors with local memory. Each server device provides a virtual resource layer through which one or more virtual processing resources can be defined and through which the physical processors of the server device can be assigned to the virtual processing resources. In use, one or more virtual processing resources is assigned to a client application for processing of data processing workloads. The resource controller then monitors the utilization of each virtual processing resource and/or any physical processor assigned to the virtual processing resource. The resource controller can dynamically adjust which, and how many, physical processors are assigned to the virtual processing resource.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: February 28, 2017
    Assignee: MAXELER TECHNOLOGIES LTD.
    Inventors: Oliver Pell, Peter Sanders, Nicolas Norvez
  • Patent number: 9514094
    Abstract: There is provided a method for processing multiple sets of data concurrently in a statically scheduled pipelined stream processor by allowing a data set to enter the pipeline while another data set is being processed. Dedicated logic units enable independent control of each of the data sets being processed.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: December 6, 2016
    Assignee: MAXELER TECHNOLOGIES LTD
    Inventors: Oliver Pell, Itay Greenspon, James Barry Spooner, Robert Gwilym Dimond, Jacob Bower, Richard Berry
  • Publication number: 20150296006
    Abstract: A system and method of dynamically provisioning virtualised computational resources in a networked computer architecture includes at least one client device operable to run one or more client applications, at least one server device and a resource controller. Each server device comprises one or more physical processors with local memory. Each server device provides a virtual resource layer through which one or more virtual processing resources can be defined and through which the physical processors of the server device can be assigned to the virtual processing resources. In use, one or more virtual processing resources is assigned to a client application for processing of data processing workloads. The resource controller then monitors the utilisation of each virtual processing resource and/or any physical processor assigned to the virtual processing resource. The resource controller can dynamically adjust which, and how many, physical processors are assigned to the virtual processing resource.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 15, 2015
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventors: Oliver PELL, Peter SANDERS, Nicolas Norvez
  • Publication number: 20150296002
    Abstract: A networked computational architecture for provisioning of virtualized computational resources. The architecture is accessible by a client application run on a client device. The architecture includes a hardware layer having a plurality of server devices, each server device having at least one physical processor having a local memory. A resource controller is provided and operable to allocate a plurality of server devices to a client application for data processing and to assign control information to the client application. The control information specifies the required allocation of a data processing workload to each server device allocated to the client application. The architecture is configured such that client applications send the data processing workload directly to each server in accordance with the control information. Thus, a networked architecture is load balanced indirectly without requiring a load balancer to be located in the data path between the client and the server.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 15, 2015
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: Oliver Pell
  • Publication number: 20150295853
    Abstract: A system and method of provisioning virtualized computational resources in a networked computer architecture includes a client device to run a client application, a server device, and a resource controller. The server device includes one or more processors having a local memory, and provides a virtual resource layer through which one or more virtual processing resources can be defined and through which one or more physical processors of said server device can be assigned to one or more of said virtual processing resources. The physical processors process at least a part of a data processing workload from said one or more client applications, each workload including input data having a static data part and a dynamic data part. The resource controller assigns a virtual processing resource to a plurality of client applications, where the input data for the workload of each client application has the same static data part.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 15, 2015
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventors: Oliver PELL, Peter SANDERS, James Barry SPOONER
  • Publication number: 20140167987
    Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventors: Oliver PELL, Stephen GIRDLESTONE, Henning MEYER
  • Publication number: 20140143744
    Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: Robert Gwilym DIMOND
  • Publication number: 20130173890
    Abstract: A method of generating a hardware design for a stream processor. The method includes defining a graph representing a processing operation designating processes to be implemented in hardware as part of the stream processor. The graph represents the processing operation in the time domain as a function of clock cycles and includes at least one data path. At least one stream offset object is provided located at a particular point in the data path.
    Type: Application
    Filed: February 27, 2013
    Publication date: July 4, 2013
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: MAXELER TECHNOLOGIES LTD.
  • Publication number: 20130139122
    Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: Oliver Pell, Jacob Alexis Bower, Richard Berry, Stefan Rolf Bach, Oliver Kadlcek
  • Publication number: 20130046912
    Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: Oliver Pell, Itay Greenspon, James Barry Spooner, Robert Gwilym Dimond
  • Publication number: 20120330638
    Abstract: Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: Oliver Pell, James Huggett
  • Publication number: 20120216019
    Abstract: There is provided embodiment of methods of generating a hardware design for a pipelined parallel stream processor.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 23, 2012
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: Jacob Alexis Bower, James Huggett, Oliver Pell
  • Publication number: 20120200315
    Abstract: Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 9, 2012
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventor: Robert Gwilym Dimond
  • Publication number: 20120159014
    Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 21, 2012
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: Robert Gwilym Dimond
  • Publication number: 20120159013
    Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 21, 2012
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: Robert Gwilym Dimond
  • Publication number: 20110320768
    Abstract: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio and/or compression scheme; selecting a copy of said set of data; and performing, on a processor, a computation using said selected copy of said set of data. By providing such a method, different compression ratios and/or compression schemes can be selected as appropriate. For example, if high precision is required in a computation, a copy of the set of data can be chosen which has a low compression ratio at the expense of processing time and memory transfer time. In the alternative, if low precision is acceptable, then the speed benefits of a high compression ratio and/or lossy compression scheme may be utilised.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: Oliver Pell, Stephen Girdlestone
  • Publication number: 20110302231
    Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimise underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: MAXELER TECHNOLOGIES, LTD.
    Inventors: James Huggett, Oliver Pell
  • Publication number: 20110145447
    Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 16, 2011
    Applicant: MAXELER TECHNOLOGIES LTD.
    Inventor: Robert Gwilym Dimond