Abstract: A method for developing TDM data with embedded control data includes obtaining signal data and control data, formatting the signal data and the control data into a plurality of channels of a DIN signal, and transmitting the DIN signal on one line of a 3-bit TDM bus. A multichannel input device includes a control extractor receptive to the three-bit TDM bus and operative to extract CNTL data from the DIN data, a DAI receptive to the 3-bit TDM bus and the channel select input and operative to develop a SIGNAL data output, and a DAC block including a DAC, the DAC block being receptive to the SIGNAL data and the CNTL data.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.

Abstract: A voltage regulator includes at least two phases, where each phase includes an inductor connected at one end to a load, a switching device that opens and closes to connect another end of the inductor to and from an input voltage; and a pulse generator that selectively closes the switching device. A phase manager module selectively triggers a pulse generator to close its switching device for a closed period when a third signal is in a first state. A comparator module selectively sets the third signal to the first state based on a ramp voltage. A ramp generator module maintains the ramp voltage at a predetermined reset voltage for a predetermined ramp reset period after the third signal transitions to the first state. The predetermined ramp reset period is less than a minimum value of the closed period. This allows the switching devices of multiple phases to be closed simultaneously.

Abstract: A differential communication system includes a first differential communication device including a differential transmitter, a second differential communication device including a differential receiver, and a differential isolator coupling the differential transmitter to the differential receiver. The differential receiver includes a comparator operative to develop waveform region information from the received waveform, a filter adapted to remove noise from the received waveform using the waveform region information, and an adaptive sampler adapted to adjust a received waveform sampling point after it has been filtered.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: In an embodiment, set forth by way of example and not limitation a USB power converter for an electronic device includes a USB bus including VBUS power line, a D? data line and a D+ data line, a variable voltage converter, a processor clock, a USB transceiver coupled to the D? data line and the D+ data line, and a processor coupled to processor clock and to the USB transceiver. Preferably, the variable voltage converter has an alternating current (AC) input, a direct current (DC) output coupled to the VBUS power line, and a voltage control input responsive to a voltage control signal to provide a plurality of voltage levels at the DC output. The process is, in this example embodiment, operative to develop the control signal based upon communication from an electronic device connected to the USB bus.

Abstract: Embodiments of the present invention provide systems, devices and methods for efficiently calculating a true RMS values (either voltage or current) of an AC signal. The RMS value is generated from both high and low frequency components of the AC signal without a high speed ADC being integrated within the system. The high frequency component is processed by calculating an average current waveform of the high frequency component and approximating a corresponding RMS value using a waveform factor. The waveform factor is effectively a scalar that relates the average current waveform of the high frequency component to an appropriate RMS value.

Abstract: A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state.

Abstract: The present invention teaches a power amplifier having two output power devices and a mechanism for switching the output path between these two power devices. The first output power device is designed for power efficient signal amplification at the power amplifier's highest output power level. The second output power device is designed for power efficient signal amplification at the output power level that the power amplifier is most likely to operate. By switching between the two power devices according to the output power level, a high level of power efficiency can be achieved across a broad range of operating states of the power amplifier.