Abstract: Systems and methods are provided for distortion redirection in phased arrays. In an electronic device configured for transmission and reception of signals and having a two-dimensional phased array, effects of distortion, corresponding to at least one processing function applied during communication of signals, on the communication of signals may be assessed, and based on the effects of distortion, one or more adjustments for mitigating the effects of distortion may be configured and applied during processing of signals. Assessing the effects of distortion may include determining one or more characteristics associated with the communication of the signals, where the one or more characteristics relate and/or are subject to the effects of the distortion, and assessing the effects of distortion based on the one or more characteristics.

Abstract: Techniques discussed herein can facilitate handshake procedures for Point-to-Multipoint (P2MP) communication in connection with various DSL (Direct Subscriber Line) technologies. Various embodiments can employ different methods of separation of signaling to arrange P2MP handshake procedures based on existing Point-to-Point (P2P) handshake procedures. Example embodiments can employ one of separation in frequency, separation in time, or separation in transmission power level.

Abstract: Aspects of methods and systems for interleaved multi-band antenna arrays are provided. An array based communications system may comprise element processors and antenna elements. Each element processor of a first plurality of element processors may communicate in a first communication band via an antenna element in a first antenna array. Each element processor of a second plurality of element processors may communicate in a second communication band via an antenna element in a second antenna array. One or more antenna elements of the second antenna array may be positioned between antenna elements of the first antenna array.

Abstract: Anti-fault injection systems and methods are disclosed. An anti-fault injection system includes a processor; a boot ROM configured to store a series of boot instructions executable by the processor; and anti-fault injection controller circuitry. The anti-fault injection controller circuitry is accessible to the processor while the processor is executing the boot instructions. The anti-fault injection controller circuitry includes interrupt/reset circuitry configured to interrupt the processor in response to a trigger and secure boot circuitry. The secure boot circuitry is configured to, in response to being accessed by the processor: determine whether the processor is executing non-secure boot instructions in error; and in response to detecting that the processor is executing non-secure boot instructions in error, provide the trigger to the interrupt/reset circuitry.

Abstract: Methods and systems are provided for power control in communications devices. Bonding of channels in communication devices may be dynamically adjusted, such as responsive to requests for bandwidth adjustment. For example, bonded channel configurations may be adjusted based on power, such as to single channel configurations (or to channel configurations with small number of channels, such as relative to current configurations) for low power operations. Components (or functions thereof) used in conjunction with receiving and/or processing bonded channels may be dynamically adjusted. Such dynamic adjustments may be performed, for example, such as to maintain required synchronization and system information to facilitate rapid data transfer resumption upon demand.

Abstract: A hardware system for signature matching in a distributed network is disclosed. The hardware system comprises a network processor and a memory. The network processor is configured to perform horizontal compression on a state table using bitmaps, wherein the state table has a plurality of states and state transitions. The processor is also configured to perform a first grouping of states of the state table using the bitmaps to generate a first one or more sets of states, perform a second grouping of states of the state table based on the first one or more sets of states and a transition threshold to generate a second one or more sets of states, perform a conquer step grouping of the states of the state table based on the second one or more sets of states and conquer criteria to generate third one or more sets of states, and generate a two dimensioned compressed state table based on the third one or more sets of states. The memory circuit is configured to store the two dimensioned compressed state table.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20?. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Abstract: A system comprises a digital predistortion circuit comprising: a first quantity of delay circuits configured to delay a signal to be predistorted; a second quantity of filter tap circuits, wherein the second quantity is smaller than the first quantity; and a delay-to-filter-taps mapping circuit that is operable to map each output of a first subset of the delay circuits to a corresponding input of the filter tap circuits. The system may comprise circuitry operable to select which of the first quantity of delay circuits is in the first subset. The selection of which of the first quantity of delay circuits is in the first subset may be based on a temperature measurement. The digital predistortion circuit may comprise cross-term generation circuitry operable to generate cross-term signals corresponding to the cross products of multiple, differently-delayed versions of a signal input to the digital predistortion circuit.

Abstract: Synchronizing methods and architectures for cable modems to transmit and receive Full Duplex (FDX) resource block allocations (RBAs) using filter switching and coordinated updating of equalization coefficients. A cable modem including a block of switchable filters, an analog front end (AFE) and a PHY/MAC System on a Chip (SoC) tuner to, at least in part, provide signals to switch the switchable filters in accordance with the RBA changes and synchronize updating tuner equalizations to match filter switching in a coordinated manner by marking received data at the AFE.

Abstract: Aspects of methods and systems for a matching circuit for a broadband bus in automotive applications are provided and may include a twisted pair wiring bus comprising a main line for coupling two end nodes and one or more stub lines, with each stub line coupling a stub node to the main line via a junction impedance on each wire in the stub line. Electrical signals may be communicated between devices coupled to the end nodes and the stub nodes. A subset of the stub nodes may be coupled to the main line in a star configuration. The junction impedance may comprise a resistor on each wire in the stub line where the resistor may have a resistance that is two to three times a nominal impedance of the main line. The junction impedance may comprise a resistor in parallel with an inductor on each wire in the stub line.

Abstract: A system comprises a plurality of antenna elements, a transmitter circuit, and first and second receiver circuits. The transmitter is operable to: transmit, via a first antenna element, a series of signals having a calibration component and each of the signals being generated with a different configuration of the transmitter circuit; and select a configuration for a future transmission based on a signal metric. The first receiver circuit is operable to: receive the signal via a second antenna element; and detect the calibration component in the signal to generate a first calibration signal. The second receiver circuit is operable to: receive the signal via a third antenna element; detect the calibration component in the signal to generate a second calibration signal; combine the first and second calibration signals to generate a combined calibration signal; and generate the signal metric based on the combined calibration signal.

Abstract: A service provider (SP) network device or system can enable a WiFi protected access 2 (WPA2) pass-through with a user equipment (UE) and define various partitions between a physical access point (pAP) and a virtual AP (vAP) based on virtual network function(s) (VNFs). The WPA2 pass-through can be an interface connection that passes through a computer premise equipment (CPE) or wireless residential gateway (GW) without modifying the data traffic and also enable different packet sizes, even if the vAP or data VNF at the SP network device is not configured to process the size, by fragmenting and defragmenting at least one of: a packet frame from the UE to the vAP, or from the vAP to the UE based on fragmentation criteria.

Abstract: Methods and systems are disclosed for multiple-input multiple-output power line communication coupling and may include a circuit for powerline communication comprising a 4-wire choke with three terminals coupled to line, neutral, and earth lines via input capacitors for receiving an alternating current (AC) power signal and radio frequency (RF) signals; a first transformer with two terminals coupled to the choke; and a coupling circuit comprising a plurality of powerline communication receivers. A first receiver of the plurality of powerline communication receivers is for receiving a first RF signal via a secondary coil of the first transformer, a second receiver of the plurality of powerline communication receivers is for receiving a second RF signal via a center terminal of a capacitor pair coupled to primary coils of the first transformer, and a third receiver of the plurality of powerline receivers is for receiving a third RF signal via a fourth terminal of the choke.

Abstract: Systems and methods are provided for supporting redundancy and outage resolution in coaxial networks with ideal taps.

Abstract: A transmitter is configured to generate a DOCSIS signal for transmission onto a frequency-selective coaxial cable. The transmitter comprises a first reverse tilt filter circuit, a digital predistortion circuit, a forward tilt filter, a wideband equalizer, a second reverse tilt filter, and a power amplifier. The responses of the tilt filters may be set based on the frequency response of the frequency-selective coaxial cable to which the transmitter is intended to be coupled. The predistortion circuit may compensate for distortion introduced by circuitry of the transmitter. The equalizer circuit may be operable to compensate for undesired linear response of other circuitry of the transmitter.

Abstract: Systems and methods are provided for utilizing remote spectrum analysis of transmit bands in communication systems. A transmit band spectrum corresponding to a transmit band used in transmitting signals may be captured. The captured transmit band spectrum may be processed, and based on such processing presence of noise, distortion, interference, etc. in the transmit band spectrum may be detected, wherein the noise, distortion, interference, etc. may be introduced by one or more other systems sharing a medium used in the transmitting of the signals. One or more characteristic associated with each instance of detected noise, distortion, interference, etc. may be determined. Reporting information, related to the detection of noise, distortion, interference, etc. and/or to the determined one or more characteristics associated with each instance of detected noise, distortion, interference, etc., may be determined, and the reported information may be sent to at least one remote system.

Abstract: Systems and methods systems and methods for efficiently and securely forming a communication network. As a non-limiting example, various aspects of the present disclosure provide systems and methods, for example utilizing a plurality of different security modes, for forming a premises-based network (e.g., a MoCA network).

Abstract: Methods and systems are disclosed for MIMO power line communication signal coupling combined with zero cross detector analog front end and may include a circuit for powerline communication including a coupling circuit and zero cross detector, where both are coupled to an input transformer that receives an alternating current (AC) power signal and radio frequency (RF) signals from line and neutral power lines via input capacitors. The coupling circuit may include a plurality of powerline communication receivers, a that receives a first RF signal via a secondary coil of the input transformer and a second that receives a second RF signal via a center terminal of a capacitor pair coupled to primary coils of the input transformer. The second receiver may comprise a second transformer. A center tap of the second transformer may be coupled to ground via an inductor. A third receiver may generate a third RF signal via the inductor.

Abstract: A system includes an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit includes a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response.