Abstract: Systems and methods systems and methods for efficiently and securely forming a communication network. As a non-limiting example, various aspects of the present disclosure provide systems and methods, for example utilizing a plurality of different security modes, for forming a premises-based network (e.g., a MoCA network).

Abstract: A system includes an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit includes a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response.

Abstract: A radar transmitter comprises orthogonal frequency division multiplexing (OFDM) symbol generation circuitry, windowing circuitry, and control circuitry. The OFDM symbol generation circuitry is operable to modulate data onto a plurality of subcarriers to generate a plurality of OFDM symbols. The windowing circuitry is configurable to support a plurality of windowing functions. The control circuitry is operable to analyze returns from a previous transmission of the radar transmitter to determine characteristics of the environment into which the previous transmission was transmitted. The control circuitry is operable to select which one of the plurality of windowing functions the windowing circuitry is to apply to each of the plurality of OFDM symbols based on the characteristics of the environment. A first one of the windowing functions may correspond to a first radiation pattern and the second one of the windowing functions may correspond to a second radiation pattern.

Abstract: Systems and methods are provided for full duplex DOCSIS cable modem echo cancellation with training. During reception of downstream signals, echo effects on downstream signals may be determined, with at least some of the echo effects corresponding to concurrently transmitted upstream signals. Echo cancellation corrections may be determined based on the determined echo effects, and the echo cancellation corrections may be applied during processing of the downstream signals. The echo cancellation corrections may include one or both of ACI (adjacent channel interference) cancellation corrections and ALI (adjacent leakage interference) cancellation correction. The echo cancellation may include or be based on preforming echo cancellation training, during active communication and based on one or both of the downstream signals and the upstream signals.

Abstract: A transmitter comprises a first peak-to-average-power ratio (PAPR) suppression circuit and a second peak-to-average-power ratio (PAPR) suppression circuit. The first PAPR suppression circuit may receive a first sequence of time-domain symbols to be transmitted, alter the first sequence based on each of a plurality of symbol ordering and/or inversion descriptors to generate a corresponding plurality of second sequences of time-domain symbols, measure a PAPR corresponding to each of the second sequences, select one of the plurality of symbol ordering and/or inversion descriptors based on the measurement of PAPR, and convey the selected one of the symbol ordering and/or inversion descriptors to the second PAPR suppression circuit. The second PAPR suppression circuit may receive the first sequence of time-domain symbols to be transmitted, and alter the first sequence based on the selected one of the symbol ordering and/or inversion descriptors to generate a reordered and/or inverted symbol sequence.

Abstract: An electronic device may be operable to sample a signal during an analog-to-digital conversion using an analog-to-digital converter in the electronic device, and the signal may comprise a wide bandwidth and a plurality of channels. The electronic device may adaptively change a sample rate of the sampling to move aliasing out of a region of one or more desired channels of the plurality of channels. The electronic device may change the sample rate using a variable oscillator in the electronic device. The change of the sample rate may comprise, for example, increasing or decreasing the sample rate by a particular percentage. In response to the change of the sample rate, the electronic device may perform, using a variable rate interpolator in the electronic device, variable rate interpolation. The variable rate interpolator may comprise, for example, a finite impulse response filter.

Abstract: A digital signal processing circuit comprises a first equalizer circuit and a second equalizer circuit. An output of the second equalizer is used as feedback to generate an equalized signal. The output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values, where the precursor values are generated based on an output of the first DFE circuit, and the postcursor values are generated independently of the output of the first DFE.

Abstract: Systems and methods for admitting new nodes into an existing network, for example a MoCA network. As a non-limiting example, various aspects of the present disclosure provide systems and methods for adding a new node to an existing network without requiring on-site manual configuration, for example utilizing communication between the new node and a network coordinator of the existing network prior to admission of the new node to the existing network.

Abstract: An array based communications system may comprise a plurality of element processors. Each element processor may comprise a combining circuit, a crest factor circuit, and a phase shifter circuit. The combining circuit may produce a weighted sum of a plurality of digital datastreams. The crest factor circuit may be operable to determine whether the weighted sum has a power above or below a power threshold. If the power is above the power threshold, the crest factor circuit is operable to reduce the power. If the power is below the power threshold, the crest factor circuit is operable to increase the power. The phase shifter circuit may introduce a phase shift to out-of-band components of the weighted sum according to the power increase or the power decrease by the crest factor circuit.

Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.

Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.

Abstract: Methods and systems for providing reduced bandwidth acquisition latency may comprise communicating a reservation request for bandwidth allocation for devices operating under a wired network protocol, where the reservation request may be sent by wired network devices via a wireless network protocol over a wireless network. Bandwidth may be allocated in the wired network for the requesting devices by a network controller. Data may be communicated with the requesting devices via the wired network. The wired network communication protocol may comprise a multimedia over cable alliance (MoCA) standard. The wireless protocol may comprise an IEEE 802.11x standard, a Bluetooth standard, and/or any non-public network protocol. The communication of the reservation request via the wireless protocol may decrease a latency of the wired network. A medium access plan (MAP) may be generated by the network controller based on the reservation request and may comprise a bandwidth allocation for the requesting devices.

Abstract: Systems and methods are provided for low-power asynchronous data links. A receiver may obtain from signals, received from a transmitter over low-power asynchronous links, recovery information embedded into the signals at the transmitter, and may determine based on the recovery information, control parameters that may be used in configuring a control signal applied during processing of the signals. The signals may be processed based on the control signal, with the processing comprising extraction of data embedded in the signals at the transmitter. The transmitter may generate, based on an input datastream, signals configured for transmission to the receiver, over low-power asynchronous data links, and may embed into the signals, the recovery information that enables determining, at the receiver, parameters relating to the signals and/or to the generating of the signals. The control parameters may comprise parameters relating to the signals and/or processing of the signals at the transmitter.

Abstract: First transmitter circuitry communicates, via bus interface circuitry, on a data bus to detect whether any second transmitter circuitry is coupled to the data bus. In instances that no second transmitter circuitry is detected as being coupled to the data bus, the first transmitter circuitry transmits beamformed signals via a first plurality of antenna elements using beamforming coefficients. In instances that second transmitter circuitry is detected as being coupled to the data bus, the first transmitter circuitry determines a phase offset between clock generation circuitry of the first transmitter circuitry and clock generation circuitry of the detected second transmitter circuitry. The first transmitter circuitry compensates the beamforming coefficients based on the determined phase offset. The first transmitter circuitry use the compensated beamforming coefficients for transmitting signals that are phase coherent with signals transmitted by the second transmitter circuitry.

Abstract: In accordance with an example implementation of this disclosure, a multifunction radar transceiver comprises a transmitter and a receiver. The transmitter is operable to modulate data onto a first radar burst, beamform the first radar burst, and transmit the first radar burst via a plurality of antenna elements. The receiver is operable to receive a reflection of the first radar burst, perform beamforming of the reflection of the first radar burst, demodulate the first radar burst to recover the data modulated on the first radar burst, and determine characteristics of an object off of which the first radar burst reflected based on characteristics of the reflection of the first radar burst.

Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

Abstract: Systems and methods are provided for utilizing low gain low noise signal amplification and ideal taps in coaxial networks. An ideal tap configured for use in coaxial networks may have a plurality of ports, one or more processing circuits configured for handling reception and transmission of signals communicated via the tap, and one or more echo cancellation circuits configured for providing echo cancellation during operations of the tap. The processing circuits are configured based on particular predefined tap performance criteria. The tap performance criteria may relate to one or more of port-to-port isolation, return loss, port-to-port gain, and up-tilt. The echo cancellation circuits may be configurable for providing the echo cancellation based on the tap performance criteria. The echo cancellation circuits may include an echo cancellation control circuit for controlling echo cancellation functions and/or operations. The echo cancellation circuits may include dedicated per-port echo cancellation circuits.

Abstract: A system comprises a multifunction radar receiver that in turn comprises processing circuitry and front-end circuitry. The front-end circuitry is operable to receive a millimeter wave burst via a plurality of antennas to generate a plurality received signals. The processing circuitry is operable to receive a first scene representation that is an aggregate of scene representations generated by one or more other radar receivers. The processing circuitry is operable to process the received signals to generate a second scene representation. The processing circuitry is operable to compare the first scene representation and the second scene representation and generate a difference scene based on the comparison. The processing circuitry is operable to generate a control signal based on the difference scene.

Abstract: A cable modem comprises transceiver circuitry and echo cancellation training circuitry. The transceiver circuitry may be operable to transmit and receive signals on a full-duplex Data Over Cable System Interface Specification (DOCSIS®) network. The echo cancellation training circuitry may be operable to: determine an echo cancellation training group to which the electronic communication device belongs; determine one or more training periods during which the echo cancellation training group is permitted to transmit training signals; and transmit an echo cancellation training signal during the determined training one or more periods and use the transmitted training signal to train echo cancellation circuitry of the cable modem.