Patents Assigned to MEARS Technologies, Inc.
  • Patent number: 9275996
    Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 1, 2016
    Assignee: MEARS TECHNOLOGIES, INC.
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Patent number: 8389974
    Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 5, 2013
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Robert John Stephenson, Marek Hytha, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Xiangyang Huang
  • Publication number: 20110215299
    Abstract: A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel including a plurality of stacked groups of layers, a source and a drain adjacent the superlattice channel, and a gate adjacent the superlattice channel. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first dopant may be in at least one region adjacent at least one of the source and drain, and a second dopant may also be in the at least one region. The second dopant may be different than the first dopant and reduce diffusion thereof.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 8, 2011
    Applicant: MEARS Technologies, Inc.
    Inventor: KALIPATNAM RAO
  • Publication number: 20110193063
    Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 11, 2011
    Applicant: MEARS TECHNOLOGIES, INC.
    Inventors: Robert J. Mears, Robert John Stephenson, Marek Hytha, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Xiangyang Huang
  • Patent number: 7928425
    Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: April 19, 2011
    Assignee: Mears Technologies, Inc.
    Inventor: Kalipatnam Vivek Rao
  • Patent number: 7880161
    Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 1, 2011
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Robert John Stephenson, Marek Hytha, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Xiangyang Huang
  • Patent number: 7863066
    Abstract: A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Robert John Stephenson, Marek Hytha, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Xiangyang Huang
  • Publication number: 20100270535
    Abstract: A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.
    Type: Application
    Filed: May 18, 2010
    Publication date: October 28, 2010
    Applicant: Mears Technologies, Inc.
    Inventors: Samed Halilov, Xiangyang Huang, Ilija Dukovski, Jean Augustin Chan Sow Fook Yiptong, Robert J. Mears, Marek Hytha, Robert John Stephenson
  • Patent number: 7812339
    Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Kalipatnam Vivek Rao
  • Patent number: 7781827
    Abstract: A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: August 24, 2010
    Assignee: Mears Technologies, Inc.
    Inventor: Kalipatnam Vivek Rao
  • Patent number: 7718996
    Abstract: A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 18, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Ilija Dukovski, Robert John Stephenson, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Robert J. Mears, Xiangyang Huang, Marek Hytha
  • Patent number: 7700447
    Abstract: A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 20, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Ilija Dukovski, Robert John Stephenson, Jean Augustin Chan Sow Fook Yiptong, Samed Halilov, Robert J. Mears, Xiangyang Huang, Marek Hytha
  • Patent number: 7659539
    Abstract: A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: February 9, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Scott A. Kreps, Kalipatnam Vivek Rao
  • Patent number: 7625767
    Abstract: A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant. The spintronic dopant may be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, the repeating structure of a superlattice may not be needed.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: December 1, 2009
    Assignee: Mears Technologies, Inc.
    Inventors: Xiangyang Huang, Samed Halilov, Jean Augustin Chan Sow Fook Yiptong, Ilija Dukovski, Marek Hytha, Robert J. Mears
  • Patent number: 7612366
    Abstract: A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 3, 2009
    Assignee: MEARS Technologies, Inc.
    Inventors: Robert J. Mears, Scott A. Kreps
  • Patent number: 7598515
    Abstract: A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 6, 2009
    Assignee: MEARS Technologies, Inc.
    Inventors: Robert J. Mears, Scott A. Kreps
  • Patent number: 7586165
    Abstract: A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: September 8, 2009
    Assignee: MEARS Technologies, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7586116
    Abstract: A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: September 8, 2009
    Assignee: MEARS Technologies, Inc.
    Inventors: Scott A. Kreps, Kalipatnam Vivek Rao
  • Patent number: 7535041
    Abstract: A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. Moreover, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: May 19, 2009
    Assignee: Mears Technologies, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7531828
    Abstract: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: May 12, 2009
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Scott A. Kreps