Abstract: A process and a package for achieving wafer scale packaging is described. A layer of silicone elastomer is deposited on the surface of a chip. Via holes through this layer connect to the top surfaces of the studs that pass through the passivating layer of the chip. In one version, the elastomer layer covers a redistribution network on a previously planarized surface of the chip. Individual chip-level networks are then connected together in the kerf so that conductive posts may be formed inside the via holes through electroplating. In another version, no redistribution network is present. A key feature of the package is that the solder bumps are not located directly over the posts but are connected to them by surface pads, thereby isolating them from stresses due to rigidity of the posts. After formation of the solder bumps, the wafer is diced into individual chips thereby isolating the individual redistribution networks.