Abstract: A Graphics Engine (GE) FIFO interface architecture that allows the transfers of reduced address information from the GE to the frame buffer is provided. The FIFO interface architecture further allows the GE to be isolated from the Memory Interface Unit (MIU) or the Central Processor Interface Unit (CIF) such that the GE can operate at a different frequency from the MIU and the CPU. Address information is provided using two flag bits End of Line (EOL) and Add One (AO). In write mode, flag bits EOL and AO are used to determine the next address in the frame buffer where processed data from the GE is to be stored. In line draw mode, flag bits EOL and AO are used to determine the address in the frame buffer for data retrieval. Such data retrieval allows a rendered line to perform background and foreground color ROP in line draw commands. Flag bit EOL indicates whether the GE needs to skip to the next scan line (e.g., the end of the current scan line has been reached).

Abstract: An apparatus that allows for high capacity and fast access command queuing without requiring excess host processor overhead clock gating apparatus that is cost efficient and allows power conservation is provided. A command and its associated data to be processed by a graphics engine are formatted as data structures and first stored in system memory. A number of these data structures can be queued in system memory at any given time. Each data structure includes a header that provides information related to the data words in the data structure such as the number of the data words involved, their destination address, and others. Using the header information provided, the command and its associated data are sequentially provided to the graphics engine for processing.

Abstract: A programmable Power Management Unit (PMU) is provided. The Power Management Unit (PMU) supports a number of different power states namely a normal power state, a software-controlled sleep power sate, a hardware-controlled sleep power state, and two register programmable power states. In the normal power state, all circuits in the integrated circuit (e.g., graphics/display controller) are enabled. In the software-controlled sleep power state, all circuits in the integrated circuit are disabled except for frame buffer memory refresh logic and part of the bus interface. In the hardware-controlled sleep power state, all circuits in the integrated circuit are disabled except for the memory interface logic. In the two register programmable power states, circuits can be selectively powered up or down as desired in a single power sequencing. Moreover, under the present invention, the interval between circuits that are being disabled or enabled in a power sequencing is also programmable.