Abstract: A multi-mixer system comprising a plurality of mixers and a filter module is provided. Each of the mixers is selectively enabled to mix an input signal with a corresponding oscillation signal to generate an output signal at an output node; and the filter module provides different frequency responses for the output signals from at least two of the output nodes of the mixers, wherein the at least two of the output nodes of the mixers are connected to different internal nodes of the filter module.

Abstract: An apparatus for performing hybrid power control in an electronic device includes a charger positioned in the electronic device, and the charger is arranged for selectively charging a battery of the electronic device. In addition, at least one portion of the charger is implemented within a charger chip. For example, the charger may include: a first terminal, positioned on the charger chip; a second terminal, positioned on the charger chip and selectively coupled to the first terminal; a third terminal, positioned on the charger chip and selectively coupled to the second terminal; a fourth terminal, positioned on the charger chip and coupled to the third terminal; a first power output path, coupled to the fourth terminal, arranged for providing a first voltage level; and a second power output path, coupled to the third terminal, arranged for selectively providing a second voltage level that is greater than the first voltage level.

Abstract: A modulation method for symbols in a frame of a compact disc includes the steps of receiving a plurality of data words, modulating each data word into a code word of a corresponding data symbol, and providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame. At least one combination of candidate merge bits is generated according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits. The combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV is selected when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and the selected combination of candidate merge bits is inserted between the two successive data symbols.