Patents Assigned to MegaChips LSI Solutions Inc.
  • Publication number: 20070126885
    Abstract: Correlation values in the vertical direction, horizontal direction and two diagonal directions are obtained in a pixel signal of RGB Bayer pattern. The correlation values are calculated using G signals. Between a first pair of the vertical and horizontal directions and a second pair of the two diagonal directions, one pair having a greater correlation difference is selected. Then, a direction having a stronger correlation is selected in the selected pair having a greater correlation difference, and pixel interpolation is performed in the selected direction. Alternatively, pixel interpolation is performed following assignment of weights in two directions of the selected pair having a greater correlation difference in accordance with the proportion of their correlations.
    Type: Application
    Filed: December 1, 2005
    Publication date: June 7, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Hiromu Hasegawa
  • Publication number: 20070120997
    Abstract: A motion detecting part detects moving regions in a plurality of frame images captured by rolling shutter type exposure, and obtains a motion vector of the moving regions. A moving region correcting part corrects the moving region in a to-be-corrected frame image of the plurality of frame images on the basis of the motion vector, information on an image-capturing time interval between the plurality of frame images, information on an exposure starting time difference resulting from the difference in position in one frame image caused by the rolling shutter type exposure and information on an exposure start sequence depending on the position in one frame image captured by the rolling shutter type exposure.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 31, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Gen Sasaki, Yusuke Nara
  • Publication number: 20070106859
    Abstract: The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Takashi OSHIKIRI
  • Publication number: 20070098273
    Abstract: When a compression part outputs JPEG data which is discrete in the time direction, the valid data is accumulated in an FIFO. When the valid data of predetermined size is accumulated in the FIFO, an encapsulation part adds markers before and after the valid data and transmits JPEG stream data to a host control module. This stream data includes encapsulated data in which the valid data is encapsulated with the markers and invalid data. The host control module stores this stream data in an SDRAM without any change. Then, by searching data for the markers, the valid data is acquired and the JPEG data is reproduced.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 3, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Gen SASAKI
  • Publication number: 20070053599
    Abstract: A rate control unit performs data truncation on a code sequence having been sorted and bit shifted as shown in FIG. 10 so that a desired noise reduction effect is achieved. The data truncation occurs in sequence from the rightmost bit. For example, in FIG. 10, data is truncated from data of bit 0 in a subband VHL4 downwardly in sequence through data of bit 0 in a subband YHH5, and so on. If the desired noise reduction effect can be achieved by truncation of up to bit data in the subband YHH1, data in those subbands in a dotted area in FIG. 10 will be truncated. If the desired noise reduction effect cannot be achieved by truncation of up to bit data in the subband YHH1, data will then be truncated from data of bit 0 in a subband VLL4 downwardly in sequence.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Yusuke Mizuno
  • Publication number: 20070053598
    Abstract: A rate control unit performs data truncation on a code sequence having been sorted and bit shifted as shown in FIG. 10 so that a desired noise reduction effect is achieved. The data truncation occurs in sequence from the rightmost bit. For example, in FIG. 10, data is truncated from data of bit 0 in a subband VHL4 downwardly in sequence through data of bit 0 in a subband YHH5, and so on. If the desired noise reduction effect can be achieved by truncation of up to bit data in the subband YHH1, data in those subbands in a dotted area in FIG. 10 will be truncated. If the desired noise reduction effect cannot be achieved by truncation of up to bit data in the subband YHH1, data will then be truncated from data of bit 0 in a subband VLL4 downwardly in sequence.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Yusuke Mizuno
  • Publication number: 20070053620
    Abstract: A rate control unit performs data truncation on a code sequence having been sorted and bit shifted as shown in FIG. 10 so that a desired noise reduction effect is achieved. The data truncation occurs in sequence from the rightmost bit. For example, in FIG. 10, data is truncated from data of bit 0 in a subband VHL4 downwardly in sequence through data of bit 0 in a subband YHH5, and so on. If the desired noise reduction effect can be achieved by truncation of up to bit data in the subband YHH1, data in those subbands in a dotted area in FIG. 10 will be truncated. If the desired noise reduction effect cannot be achieved by truncation of up to bit data in the subband YHH1, data will then be truncated from data of bit 0 in a subband VLL4 downwardly in sequence.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Yusuke Mizuno
  • Publication number: 20060262196
    Abstract: A pixel signal of Bayer pattern output from an imaging device is subjected to interpolation in a pixel interpolation circuit, and converted into a YCbCr signal in a color space conversion circuit. A chroma value calculation circuit calculates a chroma value based on the pixel signal output from the imaging device. A look-up table converts the chroma value into a suppression signal. More specifically, when the chroma value is lower than a threshold value, the look-up table outputs a value lower than 1 as the suppression signal. The suppression signal is corrected in another look-up table, and then, works on Cr and Cb signals in multipliers. A signal in a low-chroma region is thereby suppressed.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 23, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Hiromu HASEGAWA, Munehiro Mori, Nobuhiro Minami
  • Publication number: 20060228034
    Abstract: A digital diaphragm system is provided which is capable of realizing a focusing effect without using a diaphragm mechanism while greatly reducing the amount of data processing and shortening the processing time. With regions of interest set in an image a digital diaphragm effect is applied to the image by compressing the image such that the regions of interest in the image are assigned relatively larger amounts of code and are relatively in focus, such that a region of no-interest in the image is assigned a relatively smaller amount of code and is relatively out of focus, and such that lower-priority ones of the regions of interest are assigned relatively smaller amounts of code and relatively more out-of-focus.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 12, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Yusuke Mizuno, Yusuke Nara
  • Publication number: 20060222255
    Abstract: An image enhancement device is obtained which is capable of extracting, as regions of interest, still objects or objects with smaller motion vectors, or regions located out of the central area of an image. An image processing module (22) applies memorized-color correction to image data, and then stores, in an SDRAM (7) through a memory interface (26), information about the positions of the memorized-color-corrected pixels and information about the application levels (correction levels) applied to the memorized-color-corrected pixels. A mask signal generating module (23) refers to the positional information stored in the SDRAM (7) to extract the memorized-color-corrected regions of the image data as regions of interest.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 5, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Yusuke Mizuno, Yusuke Nara
  • Publication number: 20060192859
    Abstract: Concerning increasingly downsized electronic devices equipped with cameras, an object of the present invention is to achieve easy adaptability of parts. A camera module includes an image sensor and a flash memory, and a main module includes an image processing unit and an SDRAM, and the two modules are connected through a flexible cable. The flash memory stores an image processing program for controlling the image processing unit. The image processing program is a program adapted for the camera module. The flash memory also stores adjustment data that is peculiar to the camera module. When the camera function is turned on, the program is downloaded to the main module and image processing is performed.
    Type: Application
    Filed: February 8, 2006
    Publication date: August 31, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Gen SASAKI
  • Publication number: 20060159361
    Abstract: A first pixel group containing a pixel of interest, a second pixel group containing the first pixel group, and a third pixel group containing the second pixel group are defined. A first reference pixel value is calculated based on the first pixel group, and a second reference pixel value is calculated based on the third pixel group. The second pixel group is divided into two sub-groups with respect to the second reference pixel value. The sub-group containing the pixel of interest is selected as a target set. In the target set, a pixel with a pixel value close to the first reference pixel value is selected as a corrective pixel. The pixel value of the pixel of interest is replaced with the pixel value of the corrective pixel.
    Type: Application
    Filed: December 27, 2005
    Publication date: July 20, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventors: Hiromu Hasegawa, Munehiro Mori, Nobuhiro Minami
  • Publication number: 20060159357
    Abstract: A DWT unit applies wavelet transform to an input image signal to output transform coefficients, and on those transform coefficients, a quantization unit performs quantization, sorting and bit shifting with a quantization step size determined by target image quality in an image-quality control unit as well as sorting and bit shifting based on information on a region of interest specified by a ROI unit. A coefficient bit modeling unit applies bit modeling on transform coefficients outputted from the quantization unit on a bit-plane-by-bit-plane basis, and an arithmetic coding unit applies arithmetic coding on coded data inputted from the coefficient bit modeling unit. Then, a rate control unit controls the rate of coded data inputted from the arithmetic coding unit.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 20, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Yusuke Mizuno
  • Publication number: 20060114526
    Abstract: An image processing circuit inputs pixels arranged in RGB Bayer pattern. A chroma value calculation circuit calculates a chroma coefficient for evaluating chroma of a peripheral region of a target pixel. A correlation value calculation circuit calculates a correlation value for gray image and a correlation value for color image. When the chroma coefficient is higher than a first threshold value, a correlation judging method for color image and a pixel interpolation method for color image are selected. When the chroma coefficient is not higher than the first threshold value and higher than a second threshold value, a correlation judging method for gray image and the pixel interpolation method for color image are selected. When the chroma coefficient is not higher than the second threshold value, the correlation judging method for gray image and a pixel interpolation method for gray image are selected. Interpolation is executed in a pixel interpolation circuit.
    Type: Application
    Filed: November 29, 2005
    Publication date: June 1, 2006
    Applicant: MegaChips LSI Solutions Inc.
    Inventor: Hiromu Hasegawa