Abstract: A method of forming a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device on a semiconductor substrate with reduced masking steps is disclosed. In the first method, the reduced masking steps are arranged in an optimal sequence in which the gate layer is patterned first as a self-aligned mask. The gate layer includes a plurality of gate segments separated by spacings. An active mask for defining active body regions is then patterned in the spacings of the gate layer to form a combination mask. Using the combination mask as a shield, body and source regions are ion-implanted into the substrate. During the formation of the active mask, remnant material of the active mask adheres to the boundaries of the gate segments to form a spacer layer which is utilized to alleviate the cell-to-cell encroachment problem due to the side diffusion effect of the body and source regions.