Abstract: A power supply for testing an integrated circuit includes a source voltage input terminal for receiving an input voltage. A plurality of switches are coupled in parallel to the input terminal, where each of the switches is coupled to an associated resistor. Each resistor, in turn, is coupled to an output terminal that is connected to the device under test (DUT). A soft switch is connected to both the input terminal and output terminal, where the soft switch is configured to condition the output terminal voltage when one of the switches is opened or closed. The soft switch quickly stabilizes the output voltage and reduces transients in the VDUT output signal.

Abstract: A power supply for testing an integrated circuit includes a source voltage input terminal for receiving an input voltage. The power supply serves as both a DUT active power supply and an IDDQ measurement circuit, without the need for switching between separate DUT active power supply and IDDQ measurement circuits. In one embodiment, a current source output driver includes a diode across a current sensing resistor inside a feedback loop. This minimizes VDD changes when the DUT demands transient current, such as when loading IDDQ test vectors. Moreover, with decreased transient changes in VDD, dielectric absorption effects of a decoupling capacitor are reduced.

Abstract: An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.

Abstract: A novel pin electronics design and method is taught which serves to minimize the capacitive loading of the driver and load portion of the pin electronics. The driver and load circuitry are combined to form a novel driver/load circuit, thereby reducing capacitive loading, simplifying circuit structure, and improving the speed of operation of the test system and the accuracy of the test.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Abstract: A unique automatic test system (100) is provided in which timing signals are generated in a novel manner as compared with prior art test systems. All adjustments for propagation delays of timing signals are made in a digital fashion, by adjusting the digital information which defines when an analog timing signal is to be generated. Deskewing of propagation delays is performed automatically under computer control, rather than by requiring careful adjustment of hardware deskewing elements. By adjusting for propagation skews digitally, propagation skews dependent on data values (logical 0 and logical 1) can be made. Furthermore, timing signals are provided by three timing edges, rather than by a timing pulse, thereby allowing more accurate generation of timing signals.

Abstract: A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.