Abstract: A distortion compensation method for a class-D audio amplifier has the steps of connecting a compensation circuit to the class-D audio amplifier; providing a feed-forward signal from the compensation circuit to the loop filter, wherein the feed-forward signal contains replicate high-frequency components replicated from original high-frequency components of the class-D audio amplifier; and adding the feed-forward signal to those of the class-D audio amplifier. By adding the feed-forward signal, PWM-intermodulated distortion resulted from the high-frequency components is reduced. The class-D audio amplifier still maintains loop stability without affecting its phase margin.

Abstract: A buck converter includes a power stage circuit and a control circuit. The power stage circuit has a pair of switches, an output inductor, and an output capacitor. The control circuit has a current-sensing unit (CCS), an error-amplifying (EA) and transient-holding (TH) unit, a transient-optimized feedback unit (TOF), and a PWM generation unit. The CCS senses an output capacitor current. The EA with the TH receives a feedback voltage and a reference voltage to generate an error signal. The TOF receives the feedback voltage and the reference voltage to generate a proportional voltage signal by a variable gain value. The PWM generation unit receives the proportional voltage signal and a sensing voltage signal to generate a PWM signal. When the proportional voltage signal equals the sensing voltage signal, the switches are controlled by the PWM signal at an optimal time point so that transient responses are optimized.

Abstract: An analog variable-frequency controller includes a first current generator, a second current generator, a clock generator and a light/heavy load selector. The first and second current generator receive a load current signal and then output a first voltage signal and a second voltage signal, respectively. The clock generator generates a corresponding switching frequency according to the first voltage signal or the second voltage signal. The light/heavy load selector, connected with the first current generator, the second current generator and the clock generator, receives a control signal for controlling the clock generator to receive the first voltage signal or the second voltage signal. The abovementioned controller is implemented by an analog circuit, which has a lower circuit complexity, lower cost and is easy to be integrated into a switching converter.

Abstract: A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.

Abstract: A randomized thermometer-coding digital-to-analog converter (DAC) for the reduction of harmonic distortion due to non-ideal circuit mismatch is presented. The present invention introduces a new dynamic element matching technique that contains three properties of randomization, consecutive selection and less element switching activity to achieve good spurious-free dynamic range and small maximum output error. The topology uses a bank of 1-bit DAC elements, whose outputs are summed to produce a multi-level analog output. The binary digital input is encoded to be thermometer code. During a randomization period, the thermometer code is barrel-shifted to a specific starting position where the position is generated randomly. Thus, the DAC noise is randomized with less element switching activity and consecutive selection.

Abstract: A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes.

Abstract: A return-to-zero current-steering DAC is presented. The presented return-to-zero technique can isolate the analog output nodes of the DAC from the coupling of the control signals of the DAC without sacrificing speed. The topology uses a bank of return-to-zero circuits, which employs return-to-zero and isolation transistors to implement the presented return-to-zero technique.

Abstract: A method for detecting logical addresses of a nonvolatile storage medium is proposed, which defines the nonvolatile storage medium into several zones each comprising a plurality of blocks. Only an address mapping table of the first zone or a commonly used zone is built and stored in a RAM so that the system can quickly obtain logical addresses in the nonvolatile storage medium. Therefore, the effects of quick access speed and no occupied memory space can be accomplished. Moreover, the cost can be effectively lowered, and the performance of data access of the system can be enhanced.

Abstract: A method for quickly detecting the state of a nonvolatile storage medium having a plurality of blocks therein is proposed. When the system stores data in any page of a blank block, the first page thereof is simultaneously marked. When there already is data in a block to be written in, because the first page of the block is already marked, it is not necessary to mark again. Therefore, it is only necessary to directly read the first page in each block when searching the block states in the nonvolatile storage medium. The state of the nonvolatile storage medium can be quickly detected based on the existence of a mark, hence effectively enhancing the performance of data access.

Abstract: The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.

Abstract: The present invention generally relates to provide a fabrication method of a flash memory with L-shaped floating gate. The present invention utilizes a dielectric spacer on a surface of a semiconductor substrate to form a L-shaped poly spacer, which is so called the L-shaped floating gate. The respective inside portion of L-shaped floating gate is gibbous and to form a tip structure. Then, an isolating dielectric layer and a control gate are formed thereon. The control gate is covering the gibbous tip structure of the L-shaped floating gate to complete a flash memory device. The present invention is provided with a channel length, which is stably and easily controlled, and a tip structure for point discharging. Hence, the present invention can enhance the isolating effect between the control gate and the floating gate to achieve the purpose of repeating control the fabrication of the semiconductor devices.

Abstract: The present invention generally relates to a method for fabricating a post-process one-time programmable (OTP) read only memory cell (ROM cell). The OTP ROM cell has two oxide layers positioned on a semiconductor substrate and a plurality of semiconductor-implanted regions are implanted in the semiconductor substrate. Oxide layers are respectively to those semiconductor-implanted regions of the semiconductor substrate and having a window-type isolating channel region for each. Finally, a polysilicon layer is positioned on the thicker oxide layer as a gate electrode region of the OTP ROM cell. Hence, the polysilicon layer can be applied a voltage to penetrate the thinker oxide layer of the window-type isolating channel region to form a P-N junction between the semiconductor-implanted regions and the polysilicon layer and then the ROM cell is programmed.

Abstract: The structure of the FLASH device includes a first dielectric layer formed on a substrate. A floating gate with spacer profile formed on the first dielectric layer. A dielectric spacer is formed on the floating gate for isolation. A second dielectric layer is formed along the approximately vertical surface of the floating gate and the dielectric spacer and a lateral portion of the second dielectric layer laterally extends over the substrate adjacent the floating gate. A control gate is formed on the lateral portion of the second dielectric layer that laterally extends over the substrate. The control gate is formed on the lateral portion of the second dielectric layer.

Abstract: The present invention provides a fabrication method of devices like flash memory cells, which is used to fabricate a poly spacer as a floating gate. In the present invention, an oxide, a predefined and patterned first dielectric, a first poly silicon, and a second dielectric are formed in order on the surface of a semiconductor substrate. Next, anisotropic etch is performed to the second dielectric to form dielectric spacer around projective sides of the first poly silicon. The first poly silicon is then etched with the dielectric spacer as a mask. Subsequently, the first dielectric is removed. A poly spacer is thus completed. The poly spacer is used as a floating gate to complete a flash memory. A channel length of stability and easy control and tips useful for point discharge can thus be obtained so that repetitive control of fabrication of semiconductor devices can be achieved.

Abstract: The present invention relates to a memory structure and, more particularly, to a programmable memory structure erasable by electricity and a method for protecting the same. The present invention partitions a memory into a main memory section and a special memory section. A logical controller and an error detector are installed in the special memory section. When the system is booted, the special memory section will drive the error detector to detect whether the data in the main memory section is damaged. If data is lost, a backup data is read from a hard disk device via the logical controller to successfully complete booting procedures. On the other hand, this backup data will be directly duplicated into the main memory section to restore the damaged data. Thereby the data therein can be prevented from losing.

Abstract: A flat memory cell read only memory is disclosed. A flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions are planted into the substrate. A insulating layer covers on the substrate. A plurality of wordlines and metal bitlines are formed on the insulating layer. The wordlines are vertically buried to the diffusion region. A flat FET array is installed in a section between the lower sides of two adjacent buried diffusion regions and word lines. Four block selecting lines are used to control the selection of the memory cell selecting transistors for reading a selecting memory cell. Commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.