Abstract: A computing system, including a processor configured to, at development time, receive a machine learning model topology including a plurality of layers. The processor may be further configured to generate an internal representation graph of the machine learning model topology. The internal representation graph may include a plurality of internal representation layers. By performing one or more modifications to the internal representation graph, the processor may be further configured to generate an inferencer graph including a plurality of inferencer layer blocks. Each inferencer layer block may indicate an input buffer size, a logic function, and an output buffer size. At deployment time, the processor may be further configured to transmit, to a plurality of processing devices, instructions to implement the machine learning model topology with the respective input buffer sizes, logic functions, and output buffer sizes selected for the plurality of inferencer layer blocks of the inferencer graph.

Abstract: A computing system is provided, including a processor configured to generate a directed weighted graph indicating a plurality of functions configured to be executed on a plurality of communicatively connected processing devices. For each of a plurality of pairs of the functions, the processor may determine a shortest path between the pair of functions. The processor may generate a second graph indicating the plurality of pairs of functions connected by the shortest paths. The processor may receive a pipeline directed acyclic graph (DAG) specifying a data pipeline of a plurality of processing stages. The processor may determine a subgraph isomorphism between the pipeline DAG and the second graph. The processor may convey, to one or more processing devices of the plurality of processing devices, instructions to execute the plurality of processing stages as specified by the subgraph isomorphism.

Abstract: A computing system is provided, including a processor configured to receive a directed acyclic graph (DAG) template specifying a data pipeline of a plurality of processing stages. For each processing stage, the processor may be further configured to select a respective processing device of a plurality of communicatively linked processing devices. The processor may be further configured to determine a routing sequence between the plurality of processing devices according to the DAG template. The processor may be further configured to transmit a plurality of input packets encoding the plurality of processing stages to the respective processing devices selected for the processing stages as specified by the routing sequence. In response to transmitting the plurality of input packets, the processor may be further configured to receive, from a processing device of the plurality of processing devices, one or more output packets encoding a processing result of the data pipeline.