Abstract: A method and circuit for a high speed interface that enables the integration of several Content Addressable memories into a larger, Combined Content Addressable Memory with only an insignificant delay in the original response time of the individual memories. The interface provides connections to the Bus system only and no connection between different CAM devices of the system is needed, whereby the combination of one CAM and one CAM interface in a single device, such as a chip is enabled. Such chips may be used as modules for increasing the CAM Memory by directly attaching them to the Bus System without any additional interface, as known for standard memory chips such as RAM. The inventive interface may also be used for creating a hierarchical structure within a CAM device by dividing the memory cells in groups, each group being interfaced to the larger combined CAM device via an interface according to the invention.