Abstract: Memory graphics processing units (GPUs) are provided. In one aspect, a GPU for massive parallel processing of at least part of an image includes a plurality of pixel processing cores, each of the pixel processing cores configured to process a pixel of the image, and each of the pixel processing cores comprising a plurality of bit processing cores each configured to process a bit of the image and a plurality of address lines configured to provide access to the bit processing cores. The pixel processing cores are configured to process pixels of the image in parallel.

Abstract: A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.