Abstract: A serial advanced technology attachment (SATA) interface storage device. The SATA interface storage device can be used in cooperation with an electrical apparatus and comprises a substrate, a chip set, a SATA interface and a shell. The substrate has a first surface, a second surface corresponding to the first surface and a plurality of connectors between the first surface and the second surface. The chip set is disposed on the first surface. The SATA interface is disposed on the second surface and is electrically connected to the chip set via a part of the connectors so that the electrical apparatus may be electrically connected to the chip set via the SATA interface to access the chip set. The shell has a width and a thickness and defines a receiving space for receiving the substrate, the chip set and the SATA interface, where the width and the thickness conform to a micro-memory card standard.

Abstract: A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude.

Abstract: A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

Abstract: A memory device comprises a first memory cell and a second memory cell. The first memory cell includes a first transistor coupled to a bit line and the second memory cell includes a second transistor coupled to a bit line bar. The first transistor includes a first gate terminal coupled to a first word line. The second transistor includes a second gate terminal coupled to a second word line. The first transistor and the second transistor are controlled by the first word line and the second word line respectively. A first sense amplifier having an asymmetric configuration is coupled to the bit line and the bit line bar and is capable to sense a status of at least one of the bit line and the bit line bar.

Abstract: A complex memory chip is provided. The complex memory chip comprises a first pin, a second pin, a voltage generator, a flash memory, and a static random access memory (SRAM). The first pin is capable of transmitting a first voltage. The second pin is capable of transmitting a second voltage which is lower than the first voltage, so as to define a working voltage in association with the first voltage. The voltage generator generates a third voltage according to the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the SRAM operate under the working voltage. The flash memory erases data according to the third voltage.

Abstract: A method of operating a dynamic random access memory (DRAM) using a bit line and a bit line bar is disclosed. The DRAM stores data by using a charge storage device, which is coupled to the bit line via a switch device. A voltage drop occurs when the switch device is turned on. The method programs the charge storage device with a first voltage or a zero voltage in response to a power voltage reduction due to the voltage drop. For accessing the data, the bit line and the bit line bar are charged to the power voltage, the switch device is turned on and the data stored in the charge storage device is determined according to a voltage difference between the bit line and the bit line bar.

Abstract: A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing access cycles in response to the first state of the activated control signal in one part of a period, and continuously performing refresh cycles in response to the second state of the activated control signal in another part of the period.