Abstract: A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units (211) according to channels. Next, the instruction parsing units store (211) and parse the flash memory instructions corresponding to the flash memory channels, and sequentially send the flash memory control instruction to the flash memory control units (213). Then, the flash memory control units (213) send control instructions to the flash chips in the channels according to rows, and then the control instructions are processed in parallel in flash memory rows. In the present invention, the operations for each channel are performed independently in parallel, the flash memory control units (213) in the channels send the control instructions in series, and meanwhile, in each flash memory row, operations are concurrently performed in parallel.

Abstract: A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device.

Abstract: A power failure protection circuit (10) for a non-volatile semiconductor storage device includes at least an energy storage unit (C1) that serves as a backup power supply for providing backup electrical energy when a power failure occurs. During normal operation of the device, a main control unit (12) is responsible for controlling an external power input to charge the energy storage unit, for dynamically detecting the status of the energy storage unit and for using information about the status to ensure sufficient backup electrical energy for the energy storage unit. During an abnormal operation of the power supply, the main control unit (12) is responsible for discharging the energy storage unit.

Abstract: A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels.

Abstract: A method for managing blocks in a flash memory is provided, which includes dynamic and static block managing methods. In the dynamic block managing method, a blank block is selected as a swap block for write operation. During each write operation, new data and/or original data in an object block to be operated are written into the swap block, and the object block is erased. Then, a logical address of the object block is changed to be a logical address of the swap block, so that the object block served as the swap block for a next write operation. In the static block managing method, a variable seed parameter is set. Different values of the seed parameter are each associated with a logical address of a respective flash memory block.