Patents Assigned to Memory Corporation PLC
  • Patent number: 6345367
    Abstract: A fault tolerant memory system includes an array of block-erasable storage elements (12). Each block (12) of storage locations is sub-divided into sub-groups (14) of storage elements. A control information store means holds defect information for each group in each block and an address counter holds the addresses of the groups in the particular erase block being erased. A testing circuit checks whether the defect information stored in the control information store for the particular group currently addressed by the address counter indicates that the particular group contains one or more defective storage locations. If it does it increments the address counter.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: February 5, 2002
    Assignee: Memory Corporation PLC
    Inventor: Alan Welsh Sinclair
  • Patent number: 6285607
    Abstract: A memory system (10) incorporating a plurality of memory devices (42) at least one of which has a defective location. Defects are mapped in a non-volatile memory (46). Data structures are divided into portions which are respectively stored in different ones of the memory devices (42). The controller (17) of the system accesses the non-volatile memory so as to generate on a per device basis an address corresponding to a non-defective location in that device. In this system, different addresses may therefore be applied to different ones of the devices (42) when a data structure is written to or read from the memory devices.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: September 4, 2001
    Assignee: Memory Corporation PLC
    Inventor: Alan Welsh Sinclair
  • Patent number: 6069827
    Abstract: A solid state memory for emulating a disk drive comprising: translation means for translating a logical sector address to a main memory address; a main memory composed of non-volatile memory cells erasable in blocks; characterized in that a first pointer is used to point to an unwritten location in main memory, and a second pointer is used to point to the next unerased erasable block in sequence to the erasable block containing the said unwritten memory location; control means being provided to ensure that there is always at least one erasable block in the erased condition between the first and second pointers.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: May 30, 2000
    Assignee: Memory Corporation PLC
    Inventor: Alan Welsh Sinclair
  • Patent number: 6065090
    Abstract: A device for replacing defective storage locations with working storage locations comprises receiving means for receiving an incoming address for accessing a storage location, comparing means for comparing the incoming address with all of the addresses of known defective storage locations, and directing means for directing accesses to an alternative location when the incoming address matches one of the addresses of known defective storage locations. There is one alternative storage location and one comparing means for each known defective storage location. In this invention only a portion of the incoming address is used in the comparing means. In addition, each of the comparing means may use a different portion of the address for accessing a storage location.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: May 16, 2000
    Assignee: Memory Corporation PLC
    Inventor: Alexander R. Deas