Abstract: Devices, systems, and methods for controlling a shutter of a still or video camera or cellular telephone, to reduce blurring due to motion of vibrations are disclosed. The control device includes an inertial sensor for measuring acceleration, velocity and/or angular rotation and for providing data therefrom and a controller for calculating an acceleration amplitude and frequency for predicting the time between acceleration maximums. The controller opens and closes the camera shutter at a time corresponding to the predicted time between maximum accelerations as measured from a real-time acceleration maximum, negating the need for post-imaging correction.

Abstract: A wafer-level packaged IC is made by attaching a cap wafer to the front of an IC base wafer before cutting the IC base wafer, i.e. before singulating the plurality of dies on the IC base wafer. The cap wafer is mechanically attached and electrically connected to the IC base wafer, then the dies are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the front surface of the cap and electrical contact points on the IC base wafer. Optionally, the cap wafer contains one or more dies. The IC base wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without dies) can be stacked to form a “multi-story” IC. Optionally, a hermetically-sealed cavity headroom is provided.

Abstract: A system and method for testing and calibrating integrated sensor devices that improves the manufacturing test throughput of the devices. The system includes a tester, a temperature controller, and at least one probe station including a thermal chuck. The chuck can be heated to specified temperatures to achieve variable heating of a wafer, PCB, or pallet disposed thereon. The temperature controller adjusts the temperature of the chuck to a first specified level. The tester performs at least one first measurement of the output offset of each integrated sensor embodied as a die on the wafer, or as a device on the PCB or pallet. Next, the temperature controller adjusts the temperature of the chuck to a second specified level, and the tester performs at least one second measurement of the output offset of each integrated sensor at the second temperature level.

Abstract: Single chip 3-axis thermal accelerometer devices include a substrate, at least one cavity etched in the substrate, a fluid disposed in the cavity, a bridge structure suspended over an opening of the cavity, and a plurality of heater elements and temperature sensing elements disposed on the bridge structure. The substrate has a substantially planar surface defined by X and Y coordinate axes, and the bridge structure is suspended over the opening of the cavity in the X-Y plane. In one embodiment, the bridge structure is configured to position at least two of the temperature sensing elements out of the X-Y plane. The heater and temperature sensing elements are disposed on the bridge structure in optimized arrangements for providing reduced temperature coefficients and for producing output voltages having reduced DC offset and drift.

Abstract: A thermal accelerometer device that allows up to three axes of acceleration sensing. The thermal accelerometer includes a substantially planar substrate, a cavity formed in the substrate, a heater element, and at least first and second temperature sensing elements. The heater element is suspended over the cavity, and the first and second temperature sensing elements are disposed along the X or Y axis in the substrate plane on opposite sides of and at equal distances from the heater element. The thermal accelerometer employs differential temperatures detected by the temperature sensing elements to provide indications of acceleration in the X or Y directions. Further, the thermal accelerometer employs a common mode temperature detected by the temperature sensing elements to provide an indication of acceleration along a Z axis perpendicular to the X and Y axes.

Abstract: A thermal accelerometer device that provides a compensation for sensitivity variations over temperature. The thermal accelerometer includes signal conditioning circuitry operative to receive analog signals representing a differential temperature is indicative of a sensed acceleration. The signal conditioning circuitry includes serially connected A-to-D and D-to-A converters, which implement a temperature dependent function and process the received signals to provide a compensation for sensitivity variations over a range of ambient temperature. To provide a ratiometric compensation for variations in power supply voltage, a buffered voltage proportional to the supply voltage is provided as a reference voltage to the D-to-A converter. The thermal accelerometer includes a self-test circuit for verifying the integrity of a heater, temperature sensors, and circuitry included within the device.

Abstract: A chip-scale packaged IC is made by bonding one or more singulated die chips (from an IC wafer) to a common substrate, such as a single cap wafer (or a portion thereof) and cutting (singulating) the substrate to yield individual, chip-scale packaged ICs. Alternatively, each die chip is bonded to an individual, pre-cut cap. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid chip-scale packaged IC. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

Abstract: A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional “upper-level” cap wafers (with or without die) can be stacked to form a “multi-story” IC.

Abstract: An integrated convective accelerometer device. The device includes a thermal acceleration sensor having a thermopile and a heater element; control circuitry for providing closed-loop control of the thermopile common-mode voltage; an instrumentation amplifier; clock generation circuitry; voltage reference circuitry; a temperature sensor; and, output amplifiers. The device can be operated in an absolute or ratiometric mode. Further, the device is formed in a silicon substrate using standard semiconductor processes and is packaged in a standard integrated circuit package.

Abstract: A method of etching a trench in a substrate using a dry plasma etch technique that allows precise control of lateral undercut. The method includes optionally forming at least one on-chip device or micro-machined structure in a surface of a silicon substrate, and covering the surface with a masking layer. A trench pattern is then imaged in or transferred to the masking layer for subsequent etching of the substrate. Upper portions of the trench are anisotropically etched in the substrate. The trench is then semi-anisotropically etched and isotropically etched in the substrate. By modifying isotropic etching time, a controlled lateral undercut can be achieved as the trench is etched vertically in the substrate.