Abstract: A flexible Digital Signal Processor module includes a Filter unit comprising a multiplier and an adder, where the multiplier receives input from a memory and a Shift Register Lookup table. The Digital Signal Processor module may implement digital filters such as FIR or IIR filters by providing suitable filter coefficients from the memory and data values from the Shift Register Lookup table. An optional state machine may ensure synchronisation of addressing of the memory Shift Register Lookup table, and between multiple instances of the Digital Signal Processor module where these are required for a particular filter implementation. The proposed architecture offers additional modes of operation wherein operations other than filter implementations are supported.

Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

Abstract: Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranges in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

Abstract: The present invention is an innovative system and method for managing RFID elements which provides a solution for improving the efficiency, reliability and security of RFID systems. From the stand point of the users, the proposed system provides a unified interface to the raw data, giving them full and continuous access to all tags in a given RFID system. The invention enables operating a RFID system in diverse and less than optimal conditions which would otherwise compromise the integrity of the data. For instance, the proposed solution can achieve high degrees of accuracy in environments where liquid and metal distractions tender tags otherwise unreachable. In addition, the system provides means for successfully accomplishing transference of advance commands such as read, write, lock and suspend to tags which are in noisy and multi tag environments, as well as tags which are in motion or are in remote distances from a reader.