Abstract: Methods and systems for increasing the speed with which configuration data can be loaded and tested on a reconfigurable interconnect device are disclosed. A reconfigurable interconnect integrated circuit (IC), or a reconfigurable portion of an integrated circuit, is coupled to a digital storage circuit such as a shift register. A seed configuration pattern is loaded once into the digital storage circuit, which is loaded onto a first set of switches in the integrated circuit. The shift register shifts the configuration patterns by a predetermined amount, and then loads the shifted configuration pattern onto a second set of switches in the integrated circuit. Using the digital storage circuit coupled to the reconfigurable interconnect, each integrated circuit only needs to load a configuration pattern once, instead of reloading a new configuration pattern for each set of switches in the integrated circuit.

Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.

Abstract: A computer-assisted method for routing breakouts includes finding a matching for a group of pins and vias, and then routing paths between matching pin-via pairs. The matching is computed efficiently and quickly by creating convex hull data structures to represent the pins and vias, and then computing a common tangent from these convex hull structures. The endpoints of the common tangent comprise matching pin-via pairs. A matching pair is routed to find a path between a pin and via pair that achieves predefined design constraints. The method can be extended to routing wire bond connections as well.