Abstract: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.

Abstract: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.

Abstract: A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.

Abstract: Techniques for performing optical proximity correction on a layout design or portion thereof are provided with various implementations of the invention. With various implementations of the invention, movement and simulation of selected edge fragments is disabled during the optical proximity correction process. The operations of the optical proximity correction process, such as for example simulation and displacement of edge segments, is then performed for the edge fragments that remain enabled. With further implementations of the invention, a simulation site is defined for ones of the edge fragments. The operations of the optical proximity correction process, such as for example simulation and displacement of edge segments, is performed for each simulation site. Additionally, during the optical proximity correction process, the simulations sites may be moved and or removed individually based on various conditions.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus routing area is determined by the bounding box of first group of source pins and a second group of destination pins. Bus routing guidance is then generated by an automatically search engine in the bus routing area. The bus routing guidance models a bus as a skinny wire with large spacing, and it does not violate design rules. Real bus wires are generated based on the bus guidance. A bus is then automatically routed between a first group of source pins and a second group of destination pins based on the bus routing guidance.

Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in the event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.

Abstract: Configuration software is used for generating hardware-level code and data that may be used with reconfigurable/polymorphic computing platforms, such as logic emulators, and which may be used for conducting signals intelligence analysis, such as encryption/decryption processing, image analysis, etc. A user may use development tools to create visual representations of desired process algorithms, data structures, and interconnections, and system may generate intermediate data from this visual representation. The Intermediate data may be used to consult a database of predefined code segments, and segments may be assembled to generate monolithic block of hardware syhthesizable (RTL, VHDL, etc.) code for implementing the user's process in hardware. Efficiencies may be accounted for to minimize circuit components or processing time. Floating point calculations may be supported by a defined data structure that is readily implemented in hardware.

Abstract: An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.

Abstract: Techniques for improving the design of circuits, such as integrated microcircuits. A proposed circuit design is analyzed to identify design features associated with yield loss in manufactured circuits. Corrective design changes that will reduce the yield losses associated with the yield loss features then are designated. Once the corrective design changes have been determined, the corrective design changes that will optimize the manufacturing yield of the circuit are selected and incorporated into the circuit design. This analysis and revision process may then be repeated for each revised circuit design, until no further reduction in the manufacturing can be obtained.

Abstract: A method for modeling an image of a mask under illumination by a source is provided. A source map of the source is determined. For example, the source map may be a k-space diagram of plane waves for the source. The source map is then segmented into a plurality of sectors. The plurality of sectors may be pre-defined or defined by a user. A partial image intensity is then calculated for each of the plurality of sectors using a Hopkins approach. The Hopkins approach may be calculated at a point in each of the sectors, such as the center of the sectors. Then, an image intensity for the source map is determined based on the partial image intensities determined for each of the plurality of sectors. For example, each of the partial image intensities is summed to determine a total image intensity for the source map.

Abstract: Parallel operation sets for use by a software application are identified. Each parallel operation set is then provided to a master computing thread for processing, together with its associated process data. Each master computing thread will then provide its operation set to one or more slave computers based upon parallelism in the process data associated with its operation set. In this manner, the execution of operations by a software application is widely distributed among multiple networked computers based upon parallelism in both the process data used by the software and the operations executed by the software application.

Abstract: A method for determining kernels in a sum of coherent systems (SOCS) approximation is provided. Information for an object to be simulated in a manufacturing process is determined. For example, information based on geometries that are included in a layout or mask is determined. A set of kernels from a transmission cross coefficient (TCC) matrix are also determined. The set of kernels may be weighted by importance values in an order of importance. The kernels may then be re-ordered based on the information for the object. These kernels are then re-ordered in the SOCS series to reflect their order of importance. The SOCS series of kernels is then truncated at the number of kernels desired. Accordingly, by re-ordering the kernels that may be more relevant to the object to include higher weights, when the truncation occurs, the kernels that are most relevant may be included in the SOCS approximation.

Abstract: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.

Abstract: An electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.

Abstract: A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for timing and noise circuit simulations, particularly for deep sub-micron circuit design simulations. Briefly, a measurement of both total capacitance of a line and cross coupling capacitance between two lines is determined by applying predetermined voltage signals to specific circuit elements. The resulting current allows simple computation of total capacitance and cross coupling capacitance. Multiple cross coupling capacitance can be measured with a single device, thus improving the art of library generation, and the overall method is free of uncertainties related to transistor capacitance couplings.

Abstract: A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.

Abstract: Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and methods then determine if the layouts of the cells and the corresponding master cells match one another, e.g., by a layout vs. layout comparison of the design cell with the master cell to determine if the coordinates of the polygon(s) in the design cell match corresponding coordinates of the polygon(s) in the master cell. An “XOR” comparison may be used to determine if the design cell features match the corresponding master cell features. Computer-readable media may be adapted to include computer-executable instructions for performing such methods and operating such systems.