Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
Type:
Grant
Filed:
October 27, 2006
Date of Patent:
October 26, 2010
Assignee:
Mentor Graphics (Holdings) Ltd.
Inventors:
Jean-Paul Clavequin, Pascal Couteaux, Philippe Diehl
Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.
Type:
Grant
Filed:
June 10, 2003
Date of Patent:
October 23, 2007
Assignee:
Mentor Graphics (Holding) Ltd.
Inventors:
Philippe Diehl, Gilles Laurent, Frederic Reblewski
Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
Type:
Grant
Filed:
November 6, 2003
Date of Patent:
June 12, 2007
Assignee:
Mentor Graphics (Holdings) Ltd.
Inventors:
Jean-Paul Clavequin, Pascal Couteaux, Philippe Diehl
Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.
Type:
Application
Filed:
October 27, 2006
Publication date:
March 1, 2007
Applicant:
MENTOR GRAPHICS (HOLDINGS) LTD.
Inventors:
Jean-Paul Clavequin, Pascal Couteaux, Philippe Diehl