Abstract: An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source.

Abstract: An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source.

Abstract: An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration.

Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.

Abstract: An improved circuit board assembly includes a cover or other member disposed adjacent to the substrate and, for example, spaced therefrom so as to define a plenum. Self-aligning heat sinks (or other heat dissipative elements) are spring-mounted (or otherwise resiliently mounted) to the cover and, thereby, placed in thermal contact with one or more of the circuit components. Flow-diverting elements are provided, e.g., so that the overall impedance of the board substantially matches that of one or more of the other circuit boards in a common chassis. The circuit board cover can be adapted to provide thermal and/or electromagnetic emission control, as well as shock and vibration. A connector arrangement provides electrical, mechanical and/or other operational coupling between the circuit board and a chassis regardless of whether the board is disposed in a slot on a first (e.g., upper) side of a source of cooling air for the chassis or on a second (e.g., lower) opposite side of that source.

Abstract: The invention provides improved methods and systems for generation of square roots of vector and administrative operands. The methods utilize bit-manipulation operations to halve intermediate values, generated by a processor reciprocal square root operation, during a multistep process square root determination. Such methods can also multiply an original operand (whose square root is being determined) with such an intermediate value, e.g., or a halved or other value thereon. The invention also provides methods and apparatus for determination of square roots square roots of large groups of numbers by interleaving vector and administrative instructions to take advantage of necessary delays in the vector processing pipeline architecture to speed overall processing.

Abstract: A system for calculating fast Fourier transforms includes a non-final stage calculating means for repetitively performing in-place butterfly calculations for n−1 stages as well as a final stage calculating means for performing a final stage of butterfly calculations. The final stage calculating means includes a first loop and a second loop. The first loop performs a portion of the final stage butterfly calculations by iterating on a table of first loop index values consisting of values that bit-reverse into themselves. The first loop also includes control logic to select inputs for groups of butterfly calculations based on the first loop index values. The second loop performs a remaining portion of the final stage butterfly calculations by iterating on a table of second loop index value pairs consisting of two values that bit-reverse into each other.

Abstract: The invention provides improvements to multiprocessing systems of the type having a plurality of processes, each with an associated memory, and mechanisms that permit each process to access storage locations in the memory of other processes by specifying addresses (or other such indicators) associated with those locations. The improvement is characterized, according to one aspect of the invention, by an allocation element that allocates data buffers with portions encompassing data storage locations in one or more of the process memories. A mapping element generates addresses from storage location expressions that are made in terms of (i) the id.'s of processes in whose memories those locations reside, and (ii) offsets from a unique pointer—referred to as a pas_ptr—associated with each data buffer. Other improvements pertain to execution of parallel processes using such data buffering mechanisms, as well as use of semaphores and synchronization flags on multiprocessing systems.

Abstract: A multi-connector system electrically couples circuit components, such as printed circuit boards, daughtercards, integrated circuits and the like. The system includes two or more electrical connector sockets, each of which is physically coupled to a first supporting member, e.g., a rigid bar or plate. Two or more electrical connector plugs are also provided, each of which is physically coupled to a second supporting member, again, for example, a rigid bar or plate. The connector plugs and sockets can be, for example, of the VME64 160-pin variety or of any other variety and style known in the art. A jacking element, which is physically coupled with both the first and second supporting members, can be manipulated to bring them together and/or to separate them and, thereby, to couple and/or uncouple the sockets from their respective plugs.

Abstract: The invention provides a digital data processing system with improved access to information stored on a peripheral device. The system has a plurality of nodes, a peripheral device, a file system and a bypass mechanism. A first node (e.g., a client node) is connected to a second node (e.g., a server node) over a first communications pathway (e.g., a network). The second node is itself connected to a peripheral device (e.g., a disk drive) over a second communications pathway. The first node, too, is connected to the peripheral device over a third communications pathway. The file system, executing on the first and second nodes, is capable of responding to access requests generated by the first node for transferring data between that node and the peripheral device, via the second node and via the first and second communications pathways. The file system also maintains administrative information pertaining to storage on the peripheral device of data designated by such requests.

Abstract: A multicomputer is shown made up of a crossbar network to which are connected processing nodes and I/O interface nodes. The processing nodes include crossbar interface circuits that provide routing signals in local registers so that a local processor can access memory in remote processing nodes. The crossbars include circuits to establish communication paths through the crossbar networks in response to the routing signals, so that a local processor has direct access to remote memory, which is mapped into local address space. The routing signal can have a broadcast mode and can establish priority for the signal. Under some circumstances the crossbar circuit can choose between alternative paths through a crossbar. Arbitrary sized and shaped networks of crossbars can be readily implemented, and the direct memory burst transactions allow very high speed performance.

Abstract: The invention provides a system debugger for monitoring and controlling the operation of the multiprocessor. The debugger includes a view planning element that responds to operator input for generating a view signal specifying a subset of the first set of characteristics to be monitored. Likewise, a bundle planning element responds to operator input for generating a bundle signal specifying which functional units to be monitored. During operation of the multiprocessor, a runtime element monitors the operation of at least the functional units specified by the bundle signal to generate an output signal (e.g., for display on the user's monitor) representing values of the subset of characteristics specified by the view signal. The runtime element includes functionality for determining, for each of the specified functional units, which of its characteristics are in the specified subset.

Abstract: A multicomputer is shown made up of a crossbar network to which are connected processing nodes and I/O interface nodes. The processing nodes include crossbar interface circuits that provide routing signals in local registers so that a local processor can access memory in remote processing nodes. The crossbars include circuits to establish communication paths through the crossbar networks in response to the routing signals, so that a local processor has direct access to remote memory, which is mapped into local address space. The routing signal can have a broadcast mode and can establish priority for the signal. Under some circumstances the crossbar circuit can choose between alternative paths through a crossbar. Arbitrary sized and shaped networks of crossbars can be readily implemented, and the direct memory burst transactions allow very high speed performance.