Abstract: A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an expanded RISC instruction. The expanded RISC instruction contains data fields which designate indirect registers that point to emulation registers that correspond to registers in the target computer. The width of the emulation registers is at least the width of those in the target computer. However, a field in the expanded RISC instruction restricts the emulated width to that required by a particular emulated instruction. Additionally, the expanded RISC instruction contains a field which designates the emulation mode for condition codes and selects logic to match the condition codes of the target computer.

Abstract: A transmission system develops a binary encoded data train having a message and a header preceding the message. The data train is applied to a carrier frequency to modulate the carrier using FSK techniques. The header includes synch signals, one or more address signals, a message length signal and control signals separating the above signals. One or more personal receivers receive the message if responsive to one of the address signals in the header. An address signal may address a unique personal receiver, a selected group of or all such personal receivers. Each receiver is sequentially activated and deactivated, being activated to detect a synch signal. If synch signals are detected, the receiver remains activated to determine if an address signal identifies such receiver to receive the message. A received message is stored digitally and may be selectively displayed in alphanumeric characters when convenient for the recipient.