Abstract: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome.

Abstract: The present invention provides a level sensitive circuit connected to the output portion of a register, which synchronizes an asynchronous input to a clocked network driven by the CPU system clock. The level sensitive circuit ensures that the output of the synchronizing register will always be a definite binary signal, i.e. logical 0 (ground, or absence of voltage) or logical 1 (voltage). The present invention not only minimizes the occurrence of a metastable condition, but also recognizes that metastability may occur. The present invention is optimized to prevent metastability and includes a synchronizing latch having an output circuit with a feedback mechanism that effectively causes the output voltage of the register to be a valid signal only when any metastable condition has resolved itself. More particularly, the non-inverted output of the register is utilized as feedback to the level sensitive circuit.

Abstract: The invention provides a method and system for reducing capacitive coupling for transmission lines. Where there is a plurality of parallel transmission lines, a first half of the transmission lines (every second one) are inverted at their driving points, and are reinverted at a half-way point between their driving points and their receiving points, using an inverter placed halfway along the transmission line. A second half of the transmission lines are inverted at the half-way point, and are reinverted at their receiving points. Thereby, every second one of multiple transmission lines is inverted at any point in the transmission line, causing capacitive coupling to self-cancel across the entire transmission line, reducing crosstalk and speeding rise time.

Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

Abstract: A data processing system includes an instruction unit generating a program instruction. A parse unit coupled to the instruction unit receives the program instruction. The parse unit determines whether the instruction contains both load and store operations and generates first and second parcels for the instruction containing both load and store operations. A decode unit coupled to the parse unit receives the first and second parcels. The decode unit attaches an identification number to the first and second parcels, the identification number of the second parcel being determinable from the identification number of the first parcel. An issue unit coupled to the decode unit receives the first and second parcels. The issue unit issues the parcels to an instruction shelf, a load shelf, and a store shelf for instruction execution.

Abstract: Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache or from main memory, an instruction FIFO memory for storing fetched instructions from the fetch stage, and an instruction decode stage for removing instructions from the FIFO memory in accordance with relative ages of instructions stored in the FIFO memory. The decode stage examines instructions removed from the FIFO memory for trapping conditions, and flushes all younger instructions from the FIFO memory in response to identification of a trap in an instruction. The decode stage distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage immediately causes the fetch address to be changed to the appropriate trap handler address.