Abstract: A zero insertion force pin grid array socket includes a cover slidably engaged to a base and having an array of holes formed therethrough. The base has an array of corresponding passages, the passages receiving pins of an IC package inserted through corresponding holes of the cover. Contacts are mounted within the passages and include a generally tuning-fork shaped contact having torsional beams which deflect the insertion forces of the pin of the IC package which have a surface area of at least forty percent of the entire surface area of contacts. The contacts include wiping areas which are plated which have a surface area of less than an eightieth of the entire surface area of the contact. The socket cover includes a means for providing an air-gap between the socket cover and the IC package.