Abstract: New CMOS harvesting circuits are proposed that improve 2-port/multiport Register File Array circuit speed and substantially lower the energy cost of moving data along local and global bitpaths when engaging harvested data to self-limit energy dissipation. The uncertainty in BL signal development due to statistical variations in cell read current is eliminated by self-disabling action in the selected cell when the electric potential of harvested data matches the BL voltage from signal development while demanding fewer peripheral circuit transistors per column than conventional sensing schemes. Proposed bit path circuits engage harvested charge to provide immunity to disturb current noise during concurrent Read and Write access along a WL-eliminating the performance, area and energy overheads of BL keeper circuits typically required in conventional Register File arrays.

Abstract: Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0?1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Abstract: Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1?0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0?1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Abstract: A transistor memory device includes transistor storage elements storing a capacitance at each transistor storage element. Each transistor storage element includes a word line port that selects a bitcell and a bitline. Each transistor storage element performs a read data access from or a write data access to each remaining transistor storage element to increase a SNM. The device includes a harvest node configured to store a harvested charge transferred from the bitline. The transistor memory device includes a capacitor divider between the bitline and the harvest node of a first transistor storage element and configured to maintain a voltage swing on the bitline. The device further includes a harvest circuit configured to, in response to the read data access performed by the first transistor storage element, decouple the harvest node from a ground and invert a voltage equal to a potential difference between the bitline and the harvest node.

Abstract: An apparatus includes a circuit having an inverter including a power supply, an input terminal and an output terminal, and a harvest terminal electrically coupled to the output terminal. The circuit electrically couples the output terminal and the power supply, such that (1) a harvested charge is transferred from an output voltage at the output terminal to the harvest terminal in response to a high-to-low transition at the circuit and (2) a low-to-high transition at the circuit is driven using at least the harvested charge at the harvest terminal in response to the high-to-low transition.

Abstract: A transistor memory device includes storage elements storing a capacitance including (1) a capacitance at a source of PFETs, (2) a capacitance at each storage element connected to a storage node and (3) a capacitance at a gate input of inverter transistors from the plurality of transistor storage elements. Each storage element configured to perform (i) a read data access (ii) a write data access, to increase static noise margin. The transistor memory device further includes a harvest node coupled to a ground and that is configured to store a harvested charge transferred from a selected bitline to increase an output voltage at the harvest node. The transistor memory device further includes a capacitor divider configured to maintain a voltage swing on a bitline. The transistor memory device further includes a harvest circuit configured to, in response to the read data access, decouple the harvest node and invert a voltage.

Abstract: New CMOS harvesting circuits are proposed that improve 2-port/multiport Register File Array circuit speed and substantially lower the energy cost of moving data along local and global bitpaths when engaging harvested data to self-limit energy dissipation. The uncertainty in BL signal development due to statistical variations in cell read current is eliminated by self-disabling action in the selected cell when the electric potential of harvested data matches the BL voltage from signal development while demanding fewer peripheral circuit transistors per column than conventional sensing schemes. Proposed bit path circuits engage harvested charge to provide immunity to disturb current noise during concurrent Read and Write access along a wL-eliminating the performance, area and energy overheads of BL keeper circuits typically required in conventional Register File arrays.