Abstract: A method for memory management in video decoding systems that avoids some of the costs and disadvantages with video decoding systems in the prior art. Some embodiments of the present invention are especially well-suited for use with the H.264 video decoding standard. The illustrative embodiment is a memory management technique that controls which data is in the fastest memory available to a processor performing video decoding. In particular, the technique seeks to ensure that the data the processor will need is in the primary memory and expunges data that the processor will not need. The technique is based upon an analysis of predictive video decoding standards, such as H.264. By employing this technique, the illustrative embodiment ensures the expedient decoding of video frames.

Abstract: A method of parallelizing the prediction of H.264 luma blocks is disclosed. The illustrative embodiment, for example, enables the prediction of H.264 luma blocks to be performed in parallel on a single-instruction, multiple-data processor so that any two—and up to all 16 pixels—can be set simultaneously in different execution units. This is very fast and economical. The invention of formulas for enabling the parallelization of the H.264 luma blocks is noteworthy because of the diversity in the structures of the formulas for predicting the various pixels given by the H.264 standard. For example, the standard specifies fundamentally different formulas for some pixels than for others, which makes their parallelization appear impossible.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Abstract: A method and an apparatus are disclosed that seek to mitigate resource utilization during the video deblocking process of a video frame. The disclosed techniques are based on the observation that as long as the standardized filter order is preserved for those individual pixels that are filtered twice, such as corner pixels, it is unnecessary to filter across the entire video frame, first across one dimension, then across another. The video deblocker of the illustrative embodiment of the present invention deblocks the video frame by considering the pixels to be filtered on a macroblock-by-macroblock basis. In some embodiments, the deblocker deblocks the macroblock by considering the pixels to be filtered on a sub-block-by-sub-block basis. The disclosed techniques are advantageous over some techniques in the prior art because the deblocker is only required to read in all of the macroblocks in a video frame once.