Abstract: A method for convolutive encoding process and transmission by packets of a digital data series in which a set of successive n=K?1 bits are discriminated to form a current word of n bits. A stable starting binary value for the convolution encoding is defined and the current word is subjected to a convolutive encoding of depth K, at each bit value i(k) corresponding thus an encoded symbol S(k)={a(k);b(k)}. A packet of encoded symbols is formed by concatenating the encoded symbols and the stable constraint value is assigned to the convolutive encoding at the packet end. An encapsulation message the packet of encoded symbols is generated and the encapsulation message and packet of encoded symbols are transmitted in the same message for decoding and use. Decoding of the encoded symbols takes place in relation to the encapsulation message value and packet of encoded symbols length.

Abstract: A method for convolutive encoding process and transmission by packets of a digital data series in which a set of successive n=K−1 bits are discriminated to form a current word of n bits. A stable starting binary value for the convolution encoding is defined and the current word is subjected to a convolutive encoding of depth K, at each bit value i(k) corresponding thus an encoded symbol S(k)={a(k);b(k)}. A packet of encoded symbols is formed by concatenating the encoded symbols and the stable constraint value is assigned to the convolutive encoding at the packet end. An encapsulation message the packet of encoded symbols is generated and the encapsulation message and packet of encoded symbols are transmitted in the same message for decoding and use. Decoding of the encoded symbols takes place in relation to the encapsulation message value and packet of encoded symbols length.

Abstract: A high/low and low/high analogue level converter circuit for integrated circuits in which a high/low converter circuit comprises, supplied at a first voltage value, a converter module which receives a logic input signal of analogue level adapted to this first voltage value and delivers a logic signal inverted and replicated with analogue level adapted to this first voltage value, and, supplied at a second voltage value, a differential converter module which from inverted and replicated logic signals delivers a converted logic input signal with analogue level adapted to second voltage value.

Abstract: A symmetric adapter unit for switching a logic signal implemented in CMOS technology that includes a control module for transmission and non-transmission of the logic signal, receiving this logic signal and a control logic signal to deliver a first and a second asymmetric switching control signal. A bistable type switching module receives the first and the second switching control signal and delivers a logic signal adapted in phase with the logic signal or a substantially constant signal to the output terminal, constituting a high impedance output.

Abstract: A device that generates a DC reference voltage approximately equal to half a DC supply voltage. It includes an input stage forming a first potentiometric divider comprising two branches having an asymmetric behavior in response to variations in the room and/or operating temperature, and supplying a first DC voltage (NBGP), an intermediate stage forming a resistive and capacitive filter, which eliminates the dynamic component of the first DC voltage (NGBP) and supplies a second DC voltage (NARF), and an output stage forming a second potentiometric divider comprising two branches also having an asymmetric behavior of which the voltage variations are smaller than those of the first divider comprising in addition a logic inverter function, and supplying a third DC voltage (NREF), the variations of which are the inverse of those in the second DC voltage (NARF), the variations in the latter being thus compensated.

Abstract: A digital device for initializing an integrated circuit supplied from a supply voltage, which comprises a module for generating a monitored clock signal including an initial phase .phi. of pre-oscillation followed by a string of periodic pulses and a module for generating a programable initialization signal receiving this monitored clock signal and makes possible to generate an initialization signal held at a true logic value for the duration of the initial phase .phi. of pre-oscillation increased by a specified number of periods of the string of periodic pulses.

Abstract: A duration and frequency programmable electronic integrated pulse generator comprises an initialization circuit driven by a reference clock signal and an initialization/comparison signal and producing m initialization values, and a periodic count value coded on n bits. An address decoder module produces write-control bits, while a bits comparison matrix including n.times.m comparison cells each including a RAM and CAM memory cell write-addressable by the write-control bits. Each CAM cell stores a bit CAM.sub.ij of an initialization value and produces a complemented value CAM.sub.ij .sym.BL.sub.i , each RAM memory cell of address i, j produces a masking value M.sub.ij, and each comparison cell produces a value HIT.sub.ij =(CAM.sub.ij .sym.BL.sub.i)+M.sub.ij. All the cells of the same line of rank j are coupled by an OR function and produce, each output S.sub.j, a programmed pulse represented by the equation: ##EQU1## according to a harmonic periodic signal of the periodic count value.