Abstract: A circuitry (30) for on-chip power regulation is provided. The circuitry (30) comprises a memory array (31) comprising a plurality of memory cell blocks (32) arranged in rows and columns, where the memory cell blocks are clustered into a defined number of memory cell blocks (33) along the row, each cluster (33) is connected to a respective local reference line (34). In addition, the circuitry (30) comprises a plurality of sense amplifiers (40) connected to the respective memory cell blocks (32). The circuitry (30) further comprises at least one dummy memory cell block (35) additionally arranged to each cluster of memory cell blocks (33), where the dummy memory cell block (35) is connected to a main reference line (36). Moreover, the circuitry (30) comprises at least one transistor (37) arranged in between the local reference line (34) of each cluster of memory cell blocks (33) and the main reference line (36).

Abstract: A display system is provided that comprises a display panel having a plurality of pixel arrangement. Each pixel arrangement comprises at least one light emitting unit, at least one driver circuit operably coupled to the light emitting unit, and at least one digital counter operably coupled to the driver circuit. In this regard, the digital counter is configured to store a data value to be counted and to toggle a state of the driver circuit upon expiry, thereby toggling a state of the light emitting unit to perform luminance control of the pixel arrangement.

Abstract: A system is provided for facilitating an enhanced video pipeline in order to improve color perception. The system comprises a first source configured to generate a first video stream, a second source configured to generate a second video stream, and a computing device. In this context, the computing device is configured to superpose the first video stream onto the second video stream, thereby generating an output video stream. The computing device is further configured to calculate weighting factors for individual pixels or discrete pixel sets of adjacent individual pixels of the output video stream by analyzing the first video stream and/or the second video stream.